An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation

In this paper, we propose an ultra-low-voltage (ULV) SRAM in 28nm FDSOI based on a 7-T ULP bitcell that allows using only low Vt (LVT) transistors for density and speed without prohibitive leakage. The retention is based on two CMOS negative-differential resistance (NDR) structures. Thanks to importance sampling (IS) methodology, the proposed bitcell has been sized to reach low failure rate for 8-kB macro. Process voltage temperature (PVT) compensation is performed on-chip by an adaptive back biasing (ABB) generator. At 0.4V, the proposed SRAM can operate at 80 MHz and reaches access energy of 28 fJ/bit including the ABB generator in closed-loop operation.

在本文中，我们提出了一种基于28nm全耗尽绝缘体上硅（FDSOI）工艺的超低电压（ULV）静态随机存取存储器（SRAM），它采用7 - T超低功耗（ULP）位单元，能够仅使用低阈值电压（LVT）晶体管来实现密度和速度要求，且不会产生过高的泄漏电流。其数据保持功能基于两种互补金属氧化物半导体（CMOS）负微分电阻（NDR）结构。借助重要性抽样（IS）方法，所提出的位单元经过尺寸优化，使8KB的存储模块达到较低的故障率。通过自适应背偏置（ABB）发生器在芯片上进行工艺、电压和温度（PVT）补偿。在0.4V电压下，所提出的SRAM能够在80MHz频率下工作，在闭环操作中包括ABB发生器在内的访问能量达到28飞焦/位。