TOP: Towards Open & Predictable Heterogeneous SoCs

Ensuring predictability in modern real-time Systems-on-Chip (SoCs) is an increasingly critical concern for many application domains such as automotive, robotics, and industrial automation. An effective approach involves the modeling and development of hardware components, such as interconnects and shared memory resources, to evaluate or enforce their deterministic behavior. Unfortunately, these IPs are often closed-source, and these studies are limited to the single modules that must later be integrated with third-party IPs in more complex SoCs, hindering the precision and scope of modeling and compromising the overall predictability. With the coming-of-age of open-source instruction set architectures (RISC-V) and hardware, major opportunities for changing this status quo are emerging. This study introduces an innovative methodology for modeling and analyzing State-of-the-Art (SoA) open-source SoCs for low-power cyber-physical systems. Our approach models and analyzes the entire set of open-source IPs within these SoCs and then provides a comprehensive analysis of the entire architecture. We validate this methodology on a sample heterogenous low-power RISC-V architecture through RTL simulation and FPGA implementation, minimizing pessimism in bounding the service time of transactions crossing the architecture between 28% and 1%, which is considerably lower when compared to similar SoA works.

在现代实时片上系统（SoC）中确保可预测性对于汽车、机器人和工业自动化等许多应用领域来说是一个日益关键的问题。一种有效的方法涉及对硬件组件（如互连和共享内存资源）进行建模和开发，以评估或强制其确定性行为。不幸的是，这些知识产权（IP）通常是闭源的，并且这些研究仅限于单个模块，而这些模块之后必须在更复杂的SoC中与第三方IP集成，这阻碍了建模的精度和范围，并损害了整体可预测性。随着开源指令集架构（RISC - V）和硬件的成熟，改变这种现状的重大机遇正在出现。本研究引入了一种创新的方法，用于对低功耗信息物理系统的先进（SoA）开源SoC进行建模和分析。我们的方法对这些SoC中的整套开源IP进行建模和分析，然后对整个架构进行全面分析。我们通过RTL仿真和FPGA实现，在一个异构低功耗RISC - V架构示例上验证了这种方法，将跨架构事务服务时间的悲观估计降低到28%到1%之间，与类似的先进研究工作相比，这一比例相当低。