Heat Transport at Silicon Grain Boundaries

Engineering microstructural defects, like grain boundaries, offers superior control over transport properties in energy materials. However, technological advancement requires establishing microstructure‐property relations at the micron or finer scales, where most of these defects operate. Here, the first experimental evidence of thermal resistance for individual silicon grain boundaries, estimated with a Gibbs excess approach, is provided. Coincident site lattice boundaries exhibit uniform excess thermal resistance along the same boundary, but notable variations from one boundary to another. Boundaries associated with low interface energy generally exhibit lower resistances, aligning with theoretical expectations and previous simulations, but several exceptions are observed. Transmission electron microscopy reveals that factors like interface roughness and presence of nanotwinning can significantly alter the observed resistance, which ranges from ∼0 to up to ∼2.3 m2K/GW. In stark contrast, significantly larger and less uniform values ‐ from 5 to 30 m2K/GW ‐ are found for high‐angle boundaries in spark‐plasma‐sintered polycrystalline silicon. Further, finite element analysis suggests that boundary planes that strongly deviate from the sample vertical (beyond ∼45°) can show up to 3‐times larger excess resistance. Direct correlations of properties with individual defects enable the design of materials with superior thermal performance for applications in energy harvesting and heat management.

构建诸如晶界之类的微观结构缺陷，能够更好地控制能源材料的传输特性。然而，技术进步需要在微米或更小的尺度上建立微观结构 - 性能关系，因为大多数这类缺陷是在这些尺度上起作用的。在此，我们提供了首个关于单个硅晶界热阻的实验证据，该热阻是通过吉布斯过剩法估算的。重合位置点阵晶界沿同一晶界表现出均匀的过剩热阻，但不同晶界之间存在显著差异。与低界面能相关的晶界通常表现出较低的热阻，这与理论预期和先前的模拟结果相符，但也观察到了一些例外情况。透射电子显微镜显示，界面粗糙度和纳米孪晶的存在等因素会显著改变观测到的热阻，其范围从约0到高达约2.3平方米·开尔文/吉瓦。与之形成鲜明对比的是，在放电等离子烧结多晶硅的大角度晶界中，发现热阻的值要大得多且不均匀性更强，范围从5到30平方米·开尔文/吉瓦。此外，有限元分析表明，与样品垂直方向偏差较大（超过约45°）的晶界平面，其过剩热阻可能会增大至3倍。将性能与单个缺陷直接关联起来，能够设计出在能量收集和热管理应用中具有优异热性能的材料。