碳化硅基功率VDMOS器件可靠性机理及寿命模型研究

Comparing with a conventional Si-VDMOS device, a SiC-VDMOS exhibits lower on-resistance, higher breakdown voltage, faster switching speed and better thermal conduction characteristic, thereby it can simplify the topological structure of power system and reduce the system power loss and size, which is very significant to the development of power system. However, because of the low SiC/SiO2 interface barrier, big interface defect density, poor stability of SiC ohmic contact, as wells as incomplete epitaxial materials and fabrication process, the SiC-VDMOS device will face serious electrical performances degradations when it is used for a long time under high working temperature, large operation voltage and current, as well as fast switching speed conditions. Nowadays, the reliability degradation mechanisms of SiC-VDMOS under all kinds of electro-thermal stresses are not thorough and clear, and the related lifetime models are also lacked. In this project, the influences upon the reliability degradations of SiC-VDMOS from different dynamic gate alternant stresses under different operation temperatures, different freewheeling current stresses of body-diode and different switching stresses under different resistive and inductive loads will be deeply investigated, meanwhile the inner mechanisms will be explained. Moreover, the lifetime models of SiC-VDMOS under different stresses will be established to forecast the working lifetime of the device. This project will make the theoretical foundation for developing the novel power SiC-VDMOS device and the related power system with high reliability and long lifetime.

SiC基功率VDMOS器件具有导通电阻低、击穿电压高、开关速度快及热传导性好等优点，相比传统的Si基VDMOS，可简化功率电子系统拓扑结构，减小系统损耗和体积，因而对功率电子系统的发展至关重要。然而，由于SiC/SiO2界面势垒低、界面缺陷密度大、SiC欧姆接触稳定性差，以及外延材料和制备工艺仍不完善等问题，使得SiC基VDMOS在高温、高压、大电流及快速开关等极限条件下长期应用时，电学性能退化严重。目前，SiC基VDMOS在诸多电热应力下的可靠性退化机理研究尚不完善，寿命模型缺失。本课题将深入研究不同高温栅极动态交替偏置应力、寄生体二极管不同续流电流应力及不同阻性和感性负载瞬时开关应力等对SiC基VDMOS可靠性退化的影响并揭示内在机理，进而建立一套不同应力下的器件退化寿命模型，预测其工作寿命。本课题将为研制新型长寿命、高可靠的SiC基VDMOS及相关功率电子系统打下理论基础。

功率SiC-VDMOS器件具有导通电阻低、击穿电压高、开关速度快及热传导性好等优点，可简化功率电子系统的拓扑结构，减小系统损耗和体积，促进系统小型化。然而，由于SiC/SiO2界面势垒低、界面缺陷密度大及SiC欧姆接触稳定性差等问题，加之目前SiC基器件制备工艺尚不完善且外延材料仍有缺陷，使得SiC-VDMOS在高环境温度、高工作电压、大驱动电流及快速开关等极限条件下长期应用时，电学性能退化严重。.因此，本项目对SiC-VDMOS器件可靠性退化机理本质及寿命模型展开深入研究，成果简述如下：（1）基于SiC-VDMOS沟道区以及JFET区栅氧界面在不同栅压偏置下的积累、耗尽与反型状态与器件分段Cg-Vg曲线的一一对应关系，建立了适用于SiC-VDMOS的分段C-V界面损伤探测新方法；（2）明确了SiC-VDMOS在动态栅应力下Vth的退化是高电平应力阶段的电荷注入以及零电平阶段的电荷退陷共同作用的结果；（3）实验论证了SiC-VDMOS主要电学特性不随体二极管浪涌电流脉冲次数的增加而变化；（4）揭示了SiC-VDMOS在感性负载重复UIS应力下的主要退化机理为雪崩过程中JFET区栅氧界面中正电荷的注入；（5）揭示了SiC-VDMOS在阻性负载重复开关应力下的损伤机理为器件沟道区氧化层中的负电荷注入；（6）基于SiC-VDMOS在动态栅应力下的退化机理，建立了包含恢复分量在内的Vth退化表征模型；（7）基于SiC-VDMOS在重复UIS应力下的退化机理，建立了栅漏电容Cgd在重复UIS应力下的退化表征模型。.项目执行过程中，共计发表SCI论文18篇（第1作者8篇），国际会议论文2篇（均为第一作者）；申请PCT专利2项（1项第一发明人），中国发明专利9项（均为第一发明人）；此外，基于本项目成果，负责人入选2017年“装备预研教育部联合基金青年人才”和2018年 “江苏省333高层次人才培养工程—科学技术带头人”，培养博士研究生2名，硕士研究生4名。

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