面向未来通信的接收端一体化融合设计关键技术

In order to meet the 10Gbps rate requirements of 5G communication, it is necessary to study a number of new technologies, such as how to improve the capacity of the channel, increase the utilization of the spectrum and the rate of communication. The physical layer solutions, such as massive MIMO technology, millimeter wave technology, non-orthogonal multiple access technology and new channel coding technology, can effectively extend communication band, improve data rate and channel capacity, meanwhile adds high the algorithm / hardware complexity rapidly, and the traditional independent design for each function module cannot meet the system performance、circuit area and power requirements. This project focuses on the key part of receiver in the communication link, and put forwards a novel joint algorithm - hardware design method: based on the simulation and comparison analysis for error rate、 complexity and clock delay of different algorithms combination, the information constraints between different functional modules are fully used to integrated multi module co-design, thus reducing the computational complexity; based on above, optimized circuit structure is designed for the fusion algorithm with comparable performance & complexity and reducing the power、area and delay of circuit implementation as soon as possible; the FPGA based hardware verification platform is constructed to compare the different hardware processing performance. The research results have important theoretical and practical significance for the future development of communication technology.

为了达到5G通信10Gbps速率要求，需要从提升信道容量、提高频谱利用率和通信速率等多方面进行研究。目前物理层解决方案有大规模MIMO技术、毫米波技术、非正交多址接入技术以及新型信道编码技术等，在扩展通信频带，提高信道容量，提高数据率的同时带来算法/硬件复杂性的急剧增加，传统对各功能模块独立设计的方法已无法满足系统的性能、面积与功耗需求。本课题针对通信链路中计算繁重的接收端关键部分展开研究，提出算法-硬件设计一体化的研究思路: 在对多种算法组合的误码率性能、计算复杂度、处理延迟等进行仿真和对比分析的基础上，充分利用不同功能模块之间的信息约束进行多模块融合设计，降低运算复杂度；在此基础上再对性能/复杂度均衡的融合设计算法进行硬件结构优化设计，尽可能降低硬件功耗、面积开销与延时；构建基于FPGA的硬件验证平台，对比不同硬件实现方式的处理性能。研究成果对未来通信技术的发展有重要的理论和应用价值。

为了达到5G通信10Gbps速率要求，需要从提升信道容量、提高频谱利用率和通信速率等多方面进行研究。目前物理层解决方案有大规模MIMO技术、毫米波技术、非正交多址接入技术以及新型信道编码技术等，在扩展通信频带，提高信道容量，提高数据率的同时带来算法/硬件复杂性的急剧增加，传统对各功能模块独立设计的方法已无法满足系统的性能、面积与功耗需求。本课题针对通信链路中计算繁重的接收端关键部分展开研究，提出算法-硬件设计一体化的研究思路： 在对多种算法组合的误码率性能、计算复杂度、处理延迟等进行仿真和对比分析的基础上，充分利用不同功能模块之间的信息约束进行多模块融合设计，降低运算复杂度；在此基础上再对性能/复杂度均衡的融合设计算法进行硬件结构优化设计，尽可能降低硬件功耗、面积开销与延时；构建基于FPGA的硬件验证平台，对比不同硬件实现方式的处理性能。研究成果对未来通信技术的发展有重要的理论和应用价值。

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