内置自测试自动综合技术的研究

This project has been focused on Built-In Self-Test (BIST) for VLSI systems. The achievements of this project could be summarized as four aspects. Firstly, in the s design of self-testable VLSI, a parallel feedback-based BIST scheme was proposed. The analysis of topological structure of state transition graph and experimental study have revealed it efficiency. This is applicable to the self-testable design for high-speed VLSI circuits. Secondly, in the design of test pattern generator (TPG) in self-testable VLSI, a TPG scheme for the detecting of path delay fault was proposed. The structure of the proposed TPG is based on a configurable linear feedback shift register. This is applicable to the self-testing of delay fault and stuck-open fault in CMOS circuits. Thirdly, in the high-level synthesis for self-testable data path, topological structure of the strong self-adjacency and the weak self-adjacency were identified during register allocation process. This method is based on the use of test resources reusability that results in a fewer number of registers being modified to be test registers. This is applicable to high-level synthesis for self-testable data paths. Finally, in combining with other projects, testable design (including memory BIST), simulation-based design verification, test power analysis have been successfully applied to the design and test of Godson-1 CPU chip.

在数据通路综合过程中，针对内置自测试结构的要求，建立自测试电路与功能电路的共享模型，研究测试资源分配的优化方法，以期达到既能实现有效的高速自测试，又能降低自测试电路面积开销的目的。本项目研究成果的应用将有助于提高电路的自测试性，保证故障覆盖率，减少测试电路的面积开销，降低测试成本，实现自测试综合自动化。

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