机器学习芯片系统的弹性能效技术研究

Aiming at nano-scale IC, this project intends to study the design methodology with resiliency for energy efficiency that can reduce the gap between the performance requirement of complicated applications and the energy constraint of embedded platform. Machine learning algorithms are exactly heavy computation tasks, however they have the resiliency in their structures and results and thus can be more fault-tolerant under ultra-low voltage supply. In fact, to develop the optimal design of the machine learning processor, the whole design space should be explored for the resiliency with respect to energy efficiency. Therefore it is necessary to investigate how to make joint analysis for reliability and energy efficiency from the perspectives of circuit, architecture, and algorithm. To carry out this project, we will firstly study several fundamental theoretical problems, such as the mathematical model of machine learning algorithm, the parallel architecture, and the adaptive signal processing methods. Secondly we will work on the modeling about fault probability and energy efficiency in all three levels, from circuit to algorithm. Thirdly we plan to develop a design flow that enables joint analysis for reliability and energy efficiency as well as the cooperative optimization cross different design phases. Finally we will establish a prototype of machine learning processor so that the proposed design methodology can be verified and improved.

本项目着眼于解决复杂应用与嵌入式平台之间关于能效需求的矛盾与挑战，致力于探索纳米尺度集成电路的弹性能效设计方法学。机器学习算法是数据驱动的复杂计算任务，但此类算法的结构与运算结果却存在着较大的弛豫范围。这一特点使其在实现中对底层电路的故障具有较好的容忍度，可在更低的电源电压下工作。因此本项目致力于研究在电压频率过度缩放的条件下如何对可靠性与能效进行联合分析，从而利用电路、架构、算法等层次的弹性度来优化设计，实现片上机器学习系统的能效最佳化。以此为出发点，本项目首先将开展各项基础理论研究，如机器学习算法分析、并行架构变换方法、自适应信号处理等；第二将开展电路、架构、算法级的故障与能效模型研究，建立仿真实验平台；第三将开展跨层次的协同设计方法与流程研究，实现能效与可靠性的联合优化；最后通过建立机器学习的原型系统，对弹性能效设计技术进行验证和完善。

基于人工智能的物联网技术（AIoT）是未来实现社会经济变革和传统产业升级的重要驱动力，而要支撑这一领域的技术发展，如何突破能效瓶颈，实现片上机器学习是亟待解决的科学问题。本项目旨在从算法、架构和电路等层次入手探索机器学习芯片能效优化的弹性裕度，从而构建跨层次协同优化设计的方法和流程。本项目研究了电压过缩放下机器学习芯片的故障噪声容纳机制，提出了一种基于加权均值双边预测的自学习技术，通过提升容错能力充分开发能效裕度，使得心电处理电路的工作电压可低至0.41V，最高能效达到2.28pJ/cycle。研究了基于自适应滤波的心电信号运动伪影噪声消除方法，以低复杂度的电路结构实现对环境噪声的自适应能力，从而提出了相应的高能效R波检测电路设计。开展了片上机器学习系统的硬件架构优化设计研究，提出了高能效、低成本的脑电信号机器学习处理器的设计方案，实现了树深度和个数可伸缩的 Adaboost 分类器结构。围绕能效优化目标研究了算法、架构和电路多层次协同设计方法，并基于相应设计方法完成了一款面向人体姿态识别应用的机器学习处理器芯片的原型设计与验证，其能效水平领先于国际同类研究工作。

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