性能驱动可编程自重构图形处理器体系结构研究

The current GPUs (graphics processing unit) which are utilized in different applications are developed rapidly in the direction of high performance and multiple API compatibility. Many rendering algorithms with different efficiency provide high flexibility for graphics processing, so how to obtain the optimal performance according to the actual requirements is one of the bottleneck problems of graphics processor design. This project aims to establish a programmable and self-reconfigurable architecture of GPU which can obtain the optimal performance by switching the rendering algorithms fast. The research includes the following subjects: 1) to establish a performance evaluation model which takes into account the relationship comprehensively between graphics rendering factors and drawing efficiency, providing the basis for real-time self-reconfiguration of graphics hardware; 2) to establish a self-reconfiguration mechanism based on H-tree, which sends reconfigurable information through the hierarchical configuration network in a flexible control form of call instruction, and completes the reconfiguration process efficiently; 3) under the combination of performance evaluation model and reconfiguration process, establishing a two-dimensional array architecture of GPU with massive homogeneous thin-core processing elements connected locally, which realizes self-reconfiguration and programmability of computing resources by utilizing distributed instruction memory and adjacent addressing mode, and supports high efficiency array computing of coarse-grained data and coarse-grained operations. The performance-driven self-reconfigurable array processor architecture researched by this project not only can accomplish high-performance graphics rendering, but also will explore some ideas for breaking through the development bottlenecks of traditional computing architecture.

当前面向不同应用的图形处理器正朝着高性能、多种API兼容的方向迅速发展，众多效率不一的图形渲染算法使图形处理具有高度灵活性，如何根据实际需求动态获取最优性能是图形处理器设计面临的瓶颈问题之一。本项目旨在建立一种通过自主快速切换图形渲染算法获取最优性能的可编程自重构体系结构，具体包括：1）建立综合权衡图形渲染要素与渲染效率之间制约关系的性能评价模型，为图形硬件的实时自主重构提供依据；2）建立基于H-Tree的自主重构机制，通过层次化配置网络以调用指令的形式发送重构信息，实现重构过程的高效完成；3）将性能评价模型与重构过程相结合，建立基于同构轻核处理元邻接互连的图形阵列处理器，采用分布式指令存储与指令邻接寻址方式实现计算资源的可编程与自重构，支持数据粗粒度与操作粗粒度的高效阵列计算。本课题研究的性能驱动自重构阵列处理器架构不仅可以高效完成图形渲染，还将为突破传统计算架构的发展瓶颈提供一些思路。

随着高质量实时图形渲染需求的不断提升，面向不同应用的图形处理器正朝着高性能、多种API兼容的方向迅速发展，众多效率不一的图形渲染算法使图形处理具有高度灵活性，如何根据实际需求动态获取最优性能是图形处理器设计面临的瓶颈问题之一。牧村曲线表明兼顾生产标准化与应用定制化的可重构计算是体系结构的重要发展方向。本项目建立了一种通过自主快速切换图形渲染算法获取最优性能的可编程自重构体系结构。首先建立了图形渲染要素与渲染效率之间制约关系的性能评价模型，为图形硬件的实时自主重构提供依据；其次研究了基于H-Tree的重构机制HRM，通过层次化配置网络以调用指令的形式发送重构信息，实现重构过程的高效完成；进而将性能评价模型与重构过程相结合，建立基于同构轻核处理元邻接互连的图形阵列处理器PSRGPU，采用分布式指令存储与指令邻接寻址方式实现计算资源的可编程与自重构，支持数据粗粒度与操作粗粒度的高效阵列计算；最后在Xilinx的XC6VLX550T开发板上完成PSRGPU的原型系统，电路规模约527万门，编程与重构模式下的工作频率为127.75MHz和214.63MHz，可同时实现数据密集型和控制密集型操作，兼顾计算的高效性和灵活性。项目研究成果可为同类设计提供一定的借鉴与参考。

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