层次式集成电路知识产权（IP）保护指纹方法研究

With the increasing complexity of modern VLSI design, the gap between IC productivity and design capacity is becoming larger than ever before. To eliminate this gap, IP (Intellectual Property) reuse is concerned due to its efficiency and short time to market. However, the rampant piracy and infringement suffer both IP providers and IP users. IP Protection technology plays a crucial role to resist such illegal infringements. Fingerprinting technique dominates other IP protection techniques because it can not only protect the rights of IP owners, but also can trace the illegal users. Fingerprinting technique has been concerned by researchers due to its unique advantage. Based on the previous work, we combine optimization theory, IP design solving method and complex network theory, propose a novel constraint-propagation based fingerprinting method for IP protection. .The main contents of the research include: (1) research the optimization model of VLSI design, and extract the constraint hierarchy from it; (2) propose constraint-optimization based fingerprinting design solver model, and fingerprinting design distribution model; (3) propose the fingerprinting detection method applying at different design levels based on the complex network feature of the IP;(4) improve the probability of fingerprint propagation between VLSI design abstractions, and realize the hierarchical fingerprinting method for IP protection. .The proposed fingerprinting method not only guarantees the performance of IP design, but also enhances the security of the method. At the same time, it satisfies the huge demands of IP solution from the user. The hierarchical fingerprinting method can apply in the EDA design process transparently. The application of complex network theory and optimization theory shows a good paradigm in VLSI design.

集成电路的发展受知识产权（IP）盗版的制约使得IP保护技术成为当今研究热点。目前的IP保护指纹方法只集中在VLSI设计的单一层面，且存在跨层次检测困难、安全性不高等问题。本课题在IP保护的前期研究基础上，将最优化理论、IP设计求解、复杂网络理论结合在一起，提出基于约束传播的层次式IP保护指纹技术方法。主要研究内容包括：（1）研究VLSI设计的最优化模型，建立指纹保护的约束层次；（2）建立“约束综合-最优化”的指纹设计求解模型，以及抗共谋攻击能力的指纹设计分发模型；（3）基于IP设计的复杂网络特性，提出指纹的跨层次检测方法;(4）研究提高VLSI设计层次间的指纹传播方法，实现IP核的层次式指纹保护。提出的层次式指纹方法既能保证IP设计的性能,又能提高IP保护的安全性。层次式的指纹方法可透明地应用于VLSI的EDA设计流程，成果将为最优化理论及复杂网络理论在VLSI设计的应用提供借鉴。

半导体技术的巨大进步，促进了超大规模集成电路（VLSI）的飞速发展，知识产权（IP）盗版使得IP保护技术成为当今研究热点。目前的IP保护指纹方法只集中在VLSI设计的单一层面，且存在跨层次检测困难、安全性不高等问题。本课题在IP保护的前期研究基础上，将最优化理论、IP设计求解、复杂网络理论结合在一起，提出了基于约束传播的层次式IP保护指纹技术方法。课题在分析VLSI复杂网络特性的基础上，主要研究设计了VLSI设计的最优化模型，建立了指纹保护的约束层次；建立了“约束综合-最优化”的指纹设计求解模型，以及抗共谋攻击能力的指纹设计分发模型；基于IP设计的复杂网络特性，提出了指纹的跨层次检测方法；提出了提高VLSI设计层次间的指纹传播方法，实现IP核的层次式指纹保护。提出的层次式指纹方法既能保证IP设计的性能,又能提高IP保护的安全性。层次式的指纹方法可透明地应用于VLSI的EDA设计流程，成果将为最优化理论及复杂网络理论在VLSI设计的应用提供借鉴。项目执行期内，已在学术期刊及等国际会议发表及录用相关学术论文17篇，其中SCI收录7篇、EI收录4篇；授权发明专利2项，发明专利实申3项，软件著作权5项，受本项目资助培养研究生8名。

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