数据驱动异步专用处理器能效问题研究

In the era of big data, computational-intensive and memory-intensive applications, such as deep learning and computer vision, propose multiple challenges of computing power, power consumption, and flexibility for chips. Meanwhile, power consumption of the clock network inherent to synchronous circuits due to clock-driven nature and the redundant power consumption caused by clock switching make energy-efficiency difficult to improve. In this study, the data-driven asynchronous design techniques is introduced into the domain-specific processor, and a representative deep learning processor is used as the research object. From architecture modeling, simulation analysis to prototype verification, the power consumption of clock-driven synchronous specific processor under different size processes is studied, and the power consumption problems caused by the scaling of chip feature size is explored; the energy-efficiency of data-driven asynchronous specific processor under different design parameters is studied, and a hybrid asynchronous handshake protocol and data-driven fine-grained asynchronous pipeline scheme are proposed, the optimization method about energy-efficiency for asynchronous processors and the advantages of data-driven asynchronous specific processors compared to clock-driven synchronous specific processors are explored. The results can be widely used in big data processing fields, such as artificial intelligence. It can provide reference for the popularization of asynchronous specific processor design, and provide a useful reference for breaking through the energy-efficiency bottleneck of computing chip in the post-Moore era.

为了应对大数据时代深度学习、计算机视觉等计算密集型和访存密集型应用对芯片的计算能力、功耗和灵活性的多重挑战，同时解决同步电路受限于时钟驱动本质下与生俱来的时钟网络功耗以及时钟触发引起的冗余功耗导致能效难以提升的问题。本研究将数据驱动异步设计技术融入到领域专用处理器，以新型应用代表深度学习专用处理器作为研究对象。从体系结构建模、仿真分析到原型验证逐步深入，研究不同尺寸工艺下时钟驱动的同步专用处理器时钟网络功耗，探索芯片特征尺寸缩小带来的时钟网络功耗问题；研究数据驱动异步专用处理器在不同设计空间参数下的能效，提出电平型-事件型混合异步握手通信方案、数据驱动细粒度异步流水线方案，探索异步处理器的能效优化方法，探索数据驱动异步专用处理器相比时钟驱动同步专用处理器的优势。成果可广泛应用于人工智能等大数据处理领域，为异步专用处理器设计大众化提供借鉴，为突破后摩尔时代计算芯片的能效瓶颈提供有益参考。

为了满足新型应用对嵌入式处理器性能和功耗的需求，本项目将异步电路设计技术融入到领域专用处理器，以新型应用代表深度学习专用处理器作为研究对象，研究了高效异步电路设计方法学、异步自适应流水线、高能效异步RISC-V处理器架构、高能效异步DNN加速器架构等关键技术。基于FPGA开发板和基于半定制ASIC设计流程对异步RISC-V处理器、异步DNN加速器进行了原型验证和评估。异步RISC-V处理器芯片在面积和性能接近的情况下总功耗仅为同步版本的80%。异步DNN加速器与同步版本DNN加速器相比，获得了2.2倍的高性能和1.59倍的低功耗。项目成果验证了异步电路设计方法高效性及异步专用处理器的高能效，成果可广泛应用于从边缘计算到云计算中心的计算芯片领域。

内容获取失败，请点击重试