Atomic-Scale Electronics

原子级电子学

• 批准号: RGPIN-2018-05969
• 负责人: Voinigescu, Sorin
• 金额: $ 9.32万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2022
• 资助国家: 加拿大
• 起止时间: 2022-01-01 至 2023-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=751667
• 关键词: Atomic; Scale; Electronics

The progression of CMOS transistors and technology is expected to reach 5nm gate length by the year 2030. At these dimensions and beyond, many of the properties of bulk materials, including the bandgap, the energy band diagrams, and carrier mobilities, undergo dramatic changes and tunneling dominates. Coincidentally, room-temperature tunneling-based coupled quantum-dot (QD) devices, envisioned for quantum computing (QC), will also become feasible at these dimensions. Although integration density has continued to follow Moore's law due to feature size shrinking and the introduction of 3D transistor structures such as the FinFET, MOSFETs are fast approaching their scaling limits. This will affect the future evolution of both computing and wireless communication, the pillars of today's revolution in data science, machine learning and the internet of things, which rely on ever-increasing computational power and data rates, and on ambient sensing. To continue computing speed and functionality improvement beyond the end of CMOS, it is critical that a variety of channel materials and qubit structures suitable for integration in a production silicon platform be thoroughly investigated for large volume and low-cost, scalable QC qubits and integrated circuits.This proposal addresses (i) the continued scaling of computational power by exploring novel atomic-scale quantum-computing (QC) hardware in CMOS foundry processes, which can be integrated on the same die with classical CMOS logic and millimeter-wave electronics, and (ii) transceiver architectures exploiting the un-chartered 140-300 GHz frequency band for qubit spin control/readout, ambient sensing, instrumentation, and wireless communications at over 100 Gb/s.The proposed qubit ICs consist of coupled-QD electron and hole spin qubits, placed in the atomic-scale channel of multi-gate n- and p-MOSFETs, and of 60-240GHz spin control and spin readout circuits integrated on the same die. As a radical breakthrough, the fabricated qubits will feature mode energy level splitting on the order of 0.25-1 meV corresponding to Rabi frequencies in the 60-240GHz range, suitable for operation at 312 degrees Kelvin, two orders of magnitude higher than today's qubits. The tuned mm-wave circuits allow for 10-20ps spin control pulses which help to filter out wideband thermal noise and make the proposed qubits and QC logic more tolerant of short spin coherence and relaxation times. Thermal noise filtering may lead to even higher temperature operation for a given energy-level splitting.

CMOS 晶体管和技术的进步预计到 2030 年将达到 5nm 栅极长度。在这些尺寸及以上尺寸下，体材料的许多特性，包括带隙、能带图和载流子迁移率，都会发生巨大的变化，并且隧道占主导地位。巧合的是，为量子计算（QC）设想的基于室温隧道的耦合量子点（QD）器件也将在这些尺寸上变得可行。尽管由于特征尺寸缩小和 FinFET 等 3D 晶体管结构的引入，集成密度继续遵循摩尔定律，但 MOSFET 正在快速接近其尺寸极限。这将影响计算和无线通信的未来发展，而计算和无线通信是当今数据科学、机器学习和物联网革命的支柱，而这些革命依赖于不断增长的计算能力和数据速率以及环境传感。为了在 CMOS 终结之后继续提高计算速度和功能，至关重要的是，要彻底研究适合集成在生产硅平台中的各种通道材料和量子位结构，以实现大容量、低成本、可扩展的 QC 量子位和集成电路该提案解决了 (i) 通过在 CMOS 代工工艺中探索新型原子级量子计算 (QC) 硬件来持续扩展计算能力，该硬件可以与经典 CMOS 逻辑和毫米波电子器件集成在同一芯片上，以及(二) 收发器利用未特许的 140-300 GHz 频段进行量子位自旋控制/读出、环境传感、仪器仪表和超过 100 Gb/s 的无线通信的架构。拟议的量子位 IC 由耦合 QD 电子和空穴自旋量子位组成，放置在在多栅极 n- 和 p-MOSFET 的原子级通道中，以及集成在同一芯片上的 60-240GHz 自旋控制和自旋读出电路中。作为一项根本性突破，所制造的量子位将具有 0.25-1 meV 数量级的模式能级分裂，对应于 60-240GHz 范围内的拉比频率，适合在 312 开尔文温度下运行，比当今的量子位高两个数量级。调谐毫米波电路允许 10-20ps 自旋控制脉冲，这有助于滤除宽带热噪声，并使所提出​​的量子位和 QC 逻辑更能容忍短自旋相干性和弛豫时间。对于给定的能级分裂，热噪声过滤可能会导致更高的工作温度。