Development of low-voltage and low-power mixed-signal ICs using nano-scale multiple gate field-effect transistors

使用纳米级多栅极场效应晶体管开发低电压和低功耗混合信号IC

• 批准号: 342879-2012
• 负责人: ElSankary, Kamal
• 金额: $ 1.31万
• 依托单位: Dalhousie University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=572511
• 关键词: Development; low; voltage; power; mixed

The low-power and cost-effective Complementary Metal-Oxide-Semiconductor (CMOS) devices have forced the analog designers to develop integrated circuits (ICs) using digital CMOS technologies. Conventional nano-scale planar CMOS devices suffer from undesirable short-channel effects, such as high drain induced barrier lowering, substantial leakage currents due to threshold voltage roll-off, lower intrinsic gain, lower output impedance, lower dynamic range and poorer device matching. These non-idealities eventually degrade the performance of CMOS devices and pose a serious threat to ICs' performance. The Multiple gate field-effect transistors, such as Fin-shaped Field Effect Transistors (FinFETs), are emerging as the most promising replacement for planar CMOS in sub-32nm technologies. In fact, FinFET technology offers interesting features such as tight channel control to mitigate short channel effects, and steeper sub-threshold slope. Despite the advantages of multi-gate technologies, new design challenges arise particularly for analog, mixed-signal and radio frequency (RF) circuits. FinFETs suffer from larger parasitic compared to planar CMOS transistors. The narrow fin width increases the source and drain resistances and that result in degrading the high frequency and noise performance of FinFETs. Also the empty region between the gate and the source/drain causes a large increase in the fringe capacitors of the transistor and consequently reduces the speed of RF applications. FinFET devices also show new undesirable effects that have to be taking into consideration while designing analog and mixed-signal circuits; namely self-heating and hysteresis effect. Moreover, accurate physical characterization of FinFET devices represents a tremendous challenge for analog designer and new optimized layout techniques are also necessary to fully benefit from this advanced technology. As a result to enjoy the merit of multi-gate field-effect transistors, the objective of this proposal is to develop novel design methodologies for high performance analog, RF and mixed signal circuits using FinFETs.

低功率和具有成本效益的互补金属氧化物 - 氧化型（CMOS）设备已迫使模拟设计师使用数字CMOS技术开发集成电路（ICS）。常规的纳米尺度平面CMOS设备具有不良的短通道效应，例如高排水诱导的屏障降低，由于阈值电压滚动，较低的内在增益，较低的输出阻抗，较低的动态范围和较差的设备匹配而导致的大量泄漏电流。这些非理想最终降低了CMOS设备的性能，并对ICS的性能构成了严重威胁。 多个栅场效应晶体管，例如鳍状场效应晶体管（FinFET），已成为Sub-32nm Technologies中平面CMO的最有希望的替代品。实际上，FinFET技术提供了有趣的功能，例如紧密的通道控制以减轻短通道效果，以及更陡峭的子阈值。 尽管多门技术具有优势，但对于模拟，混合信号和射频（RF）电路而言，新设计挑战却引起了新的挑战。与平面CMOS晶体管相比，鳍片患有更大的寄生虫。狭窄的鳍宽度增加了源和排水电阻，这导致粉丝的高频和噪声性能降低。而且，门和源/排水之间的空区域会导致晶体管的边缘电容器大大增加，因此降低了RF应用的速度。 FinFET设备还显示出新的不良效果，这些效果在设计模拟和混合信号电路时必须考虑到这些效果。即自我加热和滞后作用。此外，FinFET设备的准确物理表征代表了模拟设计师的巨大挑战，而新的优化布局技术也是完全受益于这项先进技术的新型布局技术。 结果，享受多门田间效应晶体管的优点，该提案的目的是使用FinFET开发用于高性能模拟，RF和混合信号电路的新型设计方法。