Implementation of quantum LDPC codes and fault-tolerant logic gates in physical architectures
量子 LDPC 码和容错逻辑门在物理架构中的实现
基本信息
- 批准号:2755580
- 负责人:
- 金额:--
- 依托单位:
- 依托单位国家:英国
- 项目类别:Studentship
- 财政年份:2022
- 资助国家:英国
- 起止时间:2022 至 无数据
- 项目状态:未结题
- 来源:
- 关键词:
项目摘要
Quantum error correction (QEC) is a tool for developing quantum technologies that are robust against unavoidable errors due to unwanted interactions with the environment. QEC can be used to construct actively-corrected quantum memories [1], and the consideration of fault-tolerant gates in tandem leads to development of fault-tolerant quantum computation. Within the field of classical error correction, low density parity check (LDPC) codes are well-known linear error-correcting codes that have been studied for decades and are widely used in modern communication networks. They are characterised by a sparse parity check matrix (PCM), with key metrics being the number of physical bits, encoded bits, and distance of the code. Quantum LDPC (qLDPC) codes aim to maximise the same metrics under the different set of restrictions imposed by the quantum nature of the errors. In recent years, there have numerous developments in constructing good quantum error-correcting codes [2]: those characterised by linear (or near-linear) scaling of code distance and encoding rate with the number of physical qubits. However, these rates are only approached asymptotically [3, 4, 5], which makes their performance and implementation in real systems either unfeasible or unknown. There also exist trade-offs when considering good codes and physical restrictions, e.g. constraints on the code locality which in turn bound the encoding rate and distance [6, 7]. The aim of the PhD projects will be to work towards building good quantum error-correcting codes tailored to real architectures. The structure of the PhD is given as a series of projects under the umbrella of achieving fault tolerance and good qLDPC codes. This would involve numerical simulation of qLDPC codes, as well as understanding their construction before tailoring them towards realistic implementation. Beyond code construction, fault-tolerant implementations of logic gates will also be considered due to the crucial part they play in quantum information processing.
量子误差校正(QEC)是开发量子技术的工具,由于与环境的不良相互作用而导致不可避免的错误。 QEC可用于构建主动校正的量子记忆[1],并且在串联中对断层门的考虑会导致耐断层量子计算的发展。在经典误差校正领域内,低密度均衡检查(LDPC)代码是众所周知的线性误差校正代码,已研究了数十年,并在现代通信网络中广泛使用。它们的特征是稀疏的奇偶校验检查矩阵(PCM),关键指标是物理位,编码位和代码距离的数量。量子LDPC(QLDPC)代码旨在最大程度地提高相同的指标,这是由于错误的量子性质所施加的不同限制集。近年来,在构建良好的量子误差校正代码方面有许多发展[2]:由代码距离的线性(或接近线性)缩放的特征和用物理量子数的数量进行编码速率的特征。但是,这些速率仅渐近[3,4,5],这使得它们在实际系统中的性能和实现是不可行的或未知的。考虑良好的代码和物理限制时,也存在权衡取舍,例如对代码局部性的约束又绑定了编码速率和距离[6,7]。博士项目的目的是致力于构建针对真实体系结构量身定制的良好量子误差校正代码。博士的结构是在实现可容忍和良好的QLDPC代码的保护下,作为一系列项目。这将涉及QLDPC代码的数值模拟,并在将其定制为现实实现之前了解其结构。除了代码构建外,还将考虑逻辑门的容忍度实现,这是由于它们在量子信息处理中发挥的关键作用。
项目成果
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