NeuroSoC_A multiprocessor system on chip with in-memory neural processing unit

NeuroSoC_具有内存神经处理单元的多处理器片上系统

• 批准号: 10040829
• 金额: $ 56.05万
• 依托单位: KING'S COLLEGE LONDON
• 依托单位国家: 英国
• 项目类别: EU-Funded
• 财政年份: 2022
• 资助国家: 英国
• 起止时间: 2022 至 无数据
• 项目状态: 未结题
• 来源: https://gtr.ukri.org/projects?ref=10040829
• 关键词: NeuroSoC_A; multiprocessor; system; chip; memory

Deployment of intelligence at the edge presents many challenges because devices need to be low-cost and, as such, they are often constrained in computing capacity, memory, and energy resources. These constraints are not compatible with the need for much more advanced AI algorithms calling for Mbytes of storage and tens of GOPS per inference and call for leaner edge AI algorithms. The current state of the art for (the few) edge-AI chips relies on low-cost process technologies at 90 or 40nm and in some cases up to 16nm, with power efficiency between 1-5 TOPS/w and power densities up to 1 TOPS/mm2. Recently several industrial projects and a few products have started to surface pursing neuromorphic and in memory computing, but none of these efforts have reached a level of maturity compatible with a mass volume production and cost, and, moreover the technology base they rely on is either not scalable to more advanced nodes (flash) or, targeting AI computing algorithms whose practical applications are yet to be fully proven (e.g., spiking). The NeuroSoC approach instead is to rely on a solid, mature, and qualified reliable Phase Change Memory technology to create an industrially proven path to go past the state of the art, as such, the NeuroSoC chip pre-product demonstration of the technology will be the first of his kind worldwide. NeuroSoC’s aim is to develop an advanced Multi-Processor System on Chip prototype in FD-SOI 28nm CMOS technology that tightly integrates an AIMC IMNPU unit, a local digital processing subsystem, and functional safe multiprocessor host subsystems based on an enhanced version of existing RISC-V microprocessor implementation, while covering IMNPU security aspects holistically to tackle the requirements of a wide set of edge-AI applications. The project will leverage STMicroelectronics’s unique highdensity embedded PCM cell process technology being the denser and only such technology qualified and mature for embedded use in the industry world

在边缘部署智能会带来许多挑战，因为设备需要低成本，因此它们通常受到计算能力、内存和能源的限制，这些限制与更先进的人工智能算法的需求不兼容。每次推理需要兆字节的存储和数十个 GOPS，并需要更精简的边缘 AI 算法（少数）边缘 AI 芯片的当前技术水平依赖于 90 或 40 纳米（有时甚至更高）的低成本工艺技术。到16nm，功率效率在1-5 TOPS/w之间，功率密度高达1 TOPS/mm2。最近，一些工业项目和一些产品已经开始浮出水面，追求神经形态和内存计算，但这些努力都没有达到这样的水平。与大规模量产和成本兼容的成熟度，而且他们所依赖的技术基础要么无法扩展到更先进的节点（闪存），要么针对实际应用尚未得到充分证明的人工智能计算算法（例如，尖峰）。 NeuroSoC 方法是依靠可靠、成熟和可靠的相变存储器技术来创建一条经过工业验证的路径来超越最先进的技术，因此，NeuroSoC 芯片预产品演示NeuroSoC 的目标是采用 FD-SOI 28nm CMOS 技术开发先进的多处理器片上系统原型，紧密集成 AIMC IMNPU。该项目将提供基于现有 RISC-V 微处理器实施增强版本的单元、本地数字处理子系统和功能安全多处理器主机子系统，同时全面涵盖 IMNPU 安全方面，以满足广泛的边缘人工智能应用的要求。利用意法半导体独特的高密度嵌入式 PCM 单元工艺技术，该技术密度更高，并且只有这种技术才有资格和成熟地用于工业界的嵌入式应用