Development of local-strain technology for crystalline Ge and its application to transistors

晶体Ge局部应变技术的发展及其在晶体管中的应用

• 批准号: 23760017
• 负责人: WANG Dong
• 金额: $ 2.91万
• 依托单位: Kyushu University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Young Scientists (B)
• 财政年份: 2011
• 资助国家: 日本
• 起止时间: 2011 至 2012
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-23760017/
• 关键词: 解析・評価; 半導体物性; 電子・電気材料; 先端機能デバイス; ゲルマニウム(Ge); 歪み印加; MOSFET; 高移動度チャネル; ゲルマニウム（Ge）

To establish the technology of a strained Ge channel, after stressor formation, the dependences of strain on geometric and thermal treatment parameters were investigated by Raman spectroscopy. Defect generation, transformation, and distribution were also clarified by photoluminescence. To fabricate Ge-MOSFET, an ultra-thin SiO2/GeO2bilayer Ge-surface passivation method was developed without vacuum breaking, which showed a low interface states density (Dit) in the same degree of that for SiO2/Si. To eliminate the influence of slow-traps in the SiO2/GeO2structure, a deep level transient spectroscopy method was developed with optimized bias condition at each fixed-temperature, by which an accurate Ditevaluation was performed for GeO2/Ge. According to the result of strain evaluation, a good-quality Ge-MOSFET should be fabricated at a temperature less than 500 oC. Therefore, a low-temperature process was developed for Ge-MOSFET fabrication, by which the operation of Ge transistors was approved. Particularly, the channel mobility of p-MOSFET was four times higher than that of a Si transistor.

为了建立应变Ge通道技术，在应力源形成后，通过拉曼光谱研究了应变对几何和热处理参数的依赖性。光致发光也阐明了缺陷的产生、转变和分布。为了制造Ge-MOSFET，我们开发了一种无需破坏真空的超薄SiO2/GeO2双层Ge表面钝化方法，该方法表现出与SiO2/Si相同程度的低界面态密度(Dit)。为了消除SiO2/GeO2结构中慢陷阱的影响，开发了一种在每个固定温度下优化偏置条件的深能级瞬态光谱方法，从而对GeO2/Ge进行精确的Ditevaluation。根据应变评估的结果，高质量的Ge-MOSFET应该在低于500 oC的温度下制造。因此，开发了一种用于 Ge-MOSFET 制造的低温工艺，从而批准了 Ge 晶体管的运行。特别是，p-MOSFET的沟道迁移率是Si晶体管的四倍。

项目成果

High-quality gate-stack formation on Ge and defect termination at the interface

在 Ge 上形成高质量栅堆叠并在界面处终止缺陷

• 发表时间: 2011
• 作者: H. Nakashima;K. Hirayama;K. Yamamoto;H. Yang;D. Wang
• 通讯作者: D. Wang

Fabrication of TiN/Si Contact with Low Electron Barrier Height and Electrical Characterization of Si-On-Insulator Using Back- Gate MOSFET

低电子势垒高度的 TiN/Si 接触的制造以及使用背栅 MOSFET 的绝缘体上硅的电气特性

• 发表时间: 2012
• 期刊: Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials
• 作者: K. Asakawa;K. Yamamoto;D. Wang;H. Nakashima
• 通讯作者: H. Nakashima

High Hole-Mobility Ge p-MOSFET with HfGe Schottky Source/Drain

具有 HfGe 肖特基源极/漏极的高空穴迁移率 Ge p-MOSFET

• 发表时间: 2012
• 期刊: Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials
• 作者: T. Sada;K. Yamamoto;H. Yang;D. Wang;H. Nakashima
• 通讯作者: H. Nakashima

High Performance Ge MOSFETS with Bilayer-Passivated MOS interface

具有双层钝化 MOS 接口的高性能 Ge MOSFET

• 发表时间: 2011
• 作者: K.Yamamoto;R.Ueno;T.Yamanaka;K.Hirayama;H.Yang;D.Wang;H.Nakashima
• 通讯作者: H.Nakashima

Al/Ti/Snを用いたp形4H-SiCへのオーミックコンタクトの低温形成

使用 Al/Ti/Sn 低温形成 p 型 4H-SiC 欧姆接触

• 发表时间: 2013
• 作者: 畑山紘太;山本圭介;王冬;中島寛
• 通讯作者: 中島寛