Device Process for Integrated Systems Composed of Dislocation-Free III-V-N Alloys and Silicon

无位错III-V-N合金和硅组成的集成系统的器件工艺

基本信息

批准号：
15002007
负责人：
YONEZU Hiroo
金额：
$ 200.51万
依托单位：
Toyohashi University of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Specially Promoted Research
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2005
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-15002007/
关键词：
III-V-N alloy point defect InGaPN electric conductivity control device process MOS FET light emitting diode optoelectronic integrated system III-V-N混晶 GaPN 格子整合発光効率格子間原子 GaPNダブルヘテロ構造LED 光-電子融合シスデム光学定数伝導度制御 Si-III-V-N融

项目摘要

Basic process technologies have been developed for realizing novel optoelectronic integrated systems in a single chip, in which optical devices and electronic circuits were combined. These technologies were based on the dislocation-free heteroepitaxy of Si and III-V-N alloys.We have investigated point defects originated in N atoms in the III-V-N alloys and optical and electronic properties related to the defects. The defects were decreased by rapid thermal annealing and by suppressing the irradiation of N ions generated in an rf-plasma source. The effects led to the increase in photoluminescence intensity and the reduction of Ga interstitials. In addition, InGaPN layers with direct transition were successfully grown. It was clarified that the defects cause poor electronic conductivity. N-and p-type electronic conductivities were controlled by S and Mg doping, respectively.Si and III-V-N alloys were mutually impurities. Contamination during epitaxy was suppressed by applying a two-chamber molecular beam epitaxy system which was developed in this project. Process conditions for both devices of a Si MOS FET and a III-V-N alloy light emitting diode (LED) were optimized. Mutual diffusion between the Si and III-V-N alloy layers was suppressed by decreasing the growth temperature of a gate oxide. As a result, it became apparent that the novel optoelectronic integrated systems could be fabricated by applying a process flow followed to that of MOS integrated circuits.The composite layer of Si/III-V-N alloy double heterostructure (DH) layers was grown on a Si substrate. Elemental devices for the integrated systems, MOS FETs and LEDs, were fabricated in the topmost Si layer and the III-V-N alloy DH layer, respectively by applying the process flow for the first time. The optical output of the LED was controlled by the MOS FET. These results mean that the basic device process technologies were developed for the novel integrated systems such as ultra-parallel networks and others.

已经开发出用于在单芯片中实现新型光电集成系统的基本工艺技术，其中光学器件和电子电路相结合。这些技术基于Si和III-V-N合金的无位错异质外延。我们研究了III-V-N合金中源自N原子的点缺陷以及与缺陷相关的光学和电子性能。通过快速热退火和抑制射频等离子体源中产生的 N 离子的照射，可以减少缺陷。这些效应导致光致发光强度的增加和Ga间隙的减少。此外，还成功生长了直接过渡的InGaPN层。已澄清该缺陷导致电子传导性差。 N型和p型电子电导率分别通过S和Mg掺杂来控制。Si和III-V-N合金是相互杂质。通过应用本项目开发的两室分子束外延系统，抑制了外延过程中的污染。对 Si MOS FET 和 III-V-N 合金发光二极管 (LED) 器件的工艺条件进行了优化。通过降低栅极氧化物的生长温度来抑制Si和III-V-N合金层之间的相互扩散。结果，很明显，新型光电集成系统可以通过应用 MOS 集成电路的工艺流程来制造。Si/III-V-N 合金双异质结构 (DH) 层的复合层生长在 Si 上基材。首次应用该工艺流程，分别在最顶层的 Si 层和 III-V-N 合金 DH 层中制造了集成系统的基本器件 MOSFET 和 LED。 LED 的光输出由 MOS FET 控制。这些结果意味着为超并行网络等新型集成系统开发了基本的器件工艺技术。