Understanding and Control of Electronic Properties of Nanometer-thick Dielectric Films

纳米厚电介质薄膜电子特性的理解和控制

• 批准号: 19106005
• 负责人: TORIUMI Akira
• 金额: $ 65.81万
• 依托单位: The University of Tokyo
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (S)
• 财政年份: 2007
• 资助国家: 日本
• 起止时间: 2007 至 2011
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-19106005/
• 关键词: 電気・電子材料; 誘電体物性; 超薄膜; 表面・界面物性; 界面ダイポール; XPS; 構造相転移; Higher-k膜; GeO2; Fermi-level Pinning; ESR; 高圧酸化; ショットキーバリア高さ; High-k膜; Ge; Si-doped HfO2; HfLaOx

The gate insulator thickness is required to be thinned for enhancing semiconductor device performances. This project has aimed at the thinning the insulator thickness electrically by increasing the dielectric constant of the films instead of thinning the physical thickness. Through this research, the energy barrier heights of the insulator films with regard to Si have been obtained systematically. In addition, the stability of dielectric constant, the dipoles formed at interfaces between such films and conventional insulator(SiO_2) have been deeply investigated and modeled in terms of atom kinetics in the bulk films and at the interfaces. Furthermore, hygroscopic properties of rare-earth metal oxides have been characterized thermodynamically and the defect generation origin in GeO_2 which will be a new insulator for new semiconductor(Ge) has been also experimentally clarified.

为了提高半导体器件的性能，需要减薄栅极绝缘体的厚度。该项目的目的是通过增加薄膜的介电常数而不是减薄物理厚度来以电学方式减薄绝缘体厚度。通过这项研究，系统地获得了绝缘体薄膜对于Si的能垒高度。此外，介电常数的稳定性以及在此类薄膜与传统绝缘体（SiO_2）之间的界面处形成的偶极子已根据体膜和界面中的原子动力学进行了深入研究和建模。此外，稀土金属氧化物的吸湿特性已得到热力学表征，并且实验阐明了GeO_2（将成为新型半导体（Ge）的新绝缘体）中缺陷产生的根源。

项目成果

Observation of Dipole Layer Formed at High-k Dielectrics/SiO2 Interface with X-ray Photoelectron Spectroscopy

• DOI: 10.1143/apex.3.061501
• 发表时间: 2010-05
• 期刊: Applied Physics Express
• 影响因子: 2.3
• 作者: L. Zhu;K. Kita;T. Nishimura;K. Nagashio;Shengkai Wang;A. Toriumi

On the Origin of Anomalous VTH Shift in high-k MOSFETs

高 k MOSFET 中异常 VTH 漂移的根源

• 发表时间: 2009
• 作者: 鳥海明;喜多浩之
• 通讯作者: 喜多浩之

Materials Science-based Device Performance Engineering for Metal Gate High-k CMOS

基于材料科学的金属栅高 k CMOS 器件性能工程

• 发表时间: 2007
• 作者: A.Toriumi;K.Kita;K.Tomida;Y.Zhao;J.Widiez;T.Nabatame;H.Ota;M.Hirose
• 通讯作者: M.Hirose

XPS Analysis of High-k/SiO2/Si Stacks through Grounded Gate Metal-Estimation of Energy Levels of Electronic Structures of High-k Dielectric Films

通过接地栅金属对高 k/SiO2/Si 叠层进行 XPS 分析 - 估计高 k 介电薄膜电子结构的能级

• 发表时间: 2009
• 作者: Y.Chikata;K.Kita;T.Nishimura;K.Nagashio;A.Toriumi
• 通讯作者: A.Toriumi

UV分光エリプソメトリを用いた複素屈折率測定に基づくGe上GeO2薄膜の欠陥評価

基于紫外光谱椭圆光度法复折射率测量的 GeO2 薄膜缺陷评估

• 发表时间: 2010
• 作者: 吉田まほろ;喜多浩之;西村知紀;長汐晃輔;鳥海明
• 通讯作者: 鳥海明