Set-Valued-Logic VLSI Architecture for Highly Parallel Computation
用于高度并行计算的集值逻辑 VLSI 架构
基本信息
- 批准号:10680329
- 负责人:
- 金额:$ 2.3万
- 依托单位:
- 依托单位国家:日本
- 项目类别:Grant-in-Aid for Scientific Research (C)
- 财政年份:1998
- 资助国家:日本
- 起止时间:1998 至 2000
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Interconnection problems have been recognized as basic limitations in present-day VLSI systems. This research project is to investigate a possibility of solving the interconnection problems by employing new VLSI architectures based on multiple-valued logic (MVL) and set-valued logic (SVL). Listed below are major results of this project :1. The basic SVL gates employing binary m-sequences as information carriers were proposed.A systematic technique for synthesizing S VL circuits with the basic logic gates was investigated.2. A highly reliable SVL system employing distributed signal representation with binary m-sequences was proposed.3. A method of implementing SVL circuits using bi-directional current-mode CMOS technology was proposed. A 9x9-pixel template matching circuit for image processing was fabricated with 0.6um CMOS technology. It was shown that 30% reduction in chip area and 78% reduction in wire area could be achieved by SVL technology for 40x40-pixel template matching.4. A new type of highly parallel neural network architecture employing m-sequences as signal carriers was proposed.5. The concept of SVL was extended into a general framework of intra/inter-chip CDMA communication using orthogonal information carriers. A phase-offset-error-free CDMA technique based on multiple-valued m-sequences was investigated for efficient data transmission in VLSI systems.6. Various hardware algorithms and VLSI architectures based on MVL were also investigated to compare fundamental properties of MVL and SVL.Our initial observation shows that SVL (or CDMA) is suitable for analog signal transmission/processing as well as large-scale inter-chip communication, while MVL is suitable for digital arithmetic computation with lower processing granularity.Further investigations on MVL/SVL-based VLSI architectures for large-scale applications are being left as future research subjects.
互连问题已被认为是当今VLSI系统中的基本局限性。该研究项目是通过采用基于多价值逻辑(MVL)和Set-valued Logic(SVL)的新VLSI体系结构来研究解决互连问题的可能性。下面列出的是该项目的主要结果:1。提出了采用二进制M序列作为信息载体的基本SVL门。研究了与基本逻辑门合成S VL电路的系统技术。2。提出了使用带有二进制M序列的分布式信号表示的高度可靠的SVL系统3。提出了一种使用双向电流模式CMOS技术实施SVL电路的方法。使用0.6UM CMOS技术制造了用于图像处理的9x9像素模板匹配电路。结果表明,SVL技术可用于40x40像素模板匹配4。提出了一种采用M序列作为信号载体的新型高度平行的神经网络体系结构。5。 SVL的概念扩展到使用正交信息载体的芯片内CDMA通信的一般框架。研究了一种基于多价值M序列的无循环误差CDMA技术,以在VLSI系统中有效数据传输。6。还研究了基于MVL的各种硬件算法和VLSI架构,以比较MVL和SVL的基本属性。您的初步观察结果表明,SVL(或CDMA)适合模拟信号传输/处理/处理以及MVL的大规模交流,而MVL适用于较低的计算率,适用于MVL,适用于较低的计算。用于大规模应用的VLSI体系结构作为未来的研究对象。
项目成果
期刊论文数量(44)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Takafumi Aoki: "Beyond-binary arithmetic-Algorithms and VLSI implementations-"Interdisciplinary Information Sciences. 6・1. 75-98 (2000)
Takafumi Aoki:“超越二进制算术 - 算法和 VLSI 实现 -”跨学科信息科学 6・1(2000)。
- DOI:
- 发表时间:
- 期刊:
- 影响因子:0
- 作者:
- 通讯作者:
Takafumi Aoki: "Signed-weight arithmetic and its application to a field-programmable digital filter architecture"IEICE Transactions on Electronics. E82-C. 1687-1698 (1999)
Takafumi Aoki:“有符号权重算术及其在现场可编程数字滤波器架构中的应用”IEICE Transactions on Electronics。
- DOI:
- 发表时间:
- 期刊:
- 影响因子:0
- 作者:
- 通讯作者:
T.Aoki and T.Higuchi: "Bevond-binary arithmetic-Algorithms and implementations"Extended Abstracts of the 9th Int'l Workshop on Post-Binary Ultra-Large-Scale Integration Systems. 7-10 (2000)
T.Aoki 和 T.Higuchi:“Bevond-二进制算术-算法和实现”第九届后二进制超大规模集成系统国际研讨会的扩展摘要。
- DOI:
- 发表时间:
- 期刊:
- 影响因子:0
- 作者:
- 通讯作者:
Takafumi Aoki: "Signed-Weight Arithmetic and Its Application to a Field-Programmable Digital Filter Architecture"IEICE Transactions on Electronics. E82-C・9. 1687-1698 (1999)
Takafumi Aoki:“有符号权重算法及其在现场可编程数字滤波器架构中的应用”IEICE Transactions on Electronics。1687-1698 (1999)。
- DOI:
- 发表时间:
- 期刊:
- 影响因子:0
- 作者:
- 通讯作者:
Y.Yuminaka: "Frequency-mode set-valued logic for wave-parallel computing-Design and experimental realization" Multiple-Valued Logic. 3・4. 301-332 (1998)
Y.Yuminaka:“波并行计算的频率模式集值逻辑 - 设计和实验实现”多值逻辑 3・4(1998)。
- DOI:
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- 影响因子:0
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AOKI Takafumi其他文献
AOKI Takafumi的其他文献
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{{ truncateString('AOKI Takafumi', 18)}}的其他基金
Development of High-Accuracy Image Matching Technology Using Phase Information and Its Applications
利用相位信息的高精度图像匹配技术的发展及其应用
- 批准号:
24300067 - 财政年份:2012
- 资助金额:
$ 2.3万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Development of Image-Based Person Identification Technology Supporting Forengic Odontology and Medicine
支持法医牙科学和医学的基于图像的人员识别技术的开发
- 批准号:
24650074 - 财政年份:2012
- 资助金额:
$ 2.3万 - 项目类别:
Grant-in-Aid for Challenging Exploratory Research
Applications of High-Accuracy Image Matching Technology Breaking the Limit of Pixel Resolution
高精度图像匹配技术应用突破像素分辨率极限
- 批准号:
21300059 - 财政年份:2009
- 资助金额:
$ 2.3万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Development of Image Processing Technology Breaking the Limit of Pixel Resolution
图像处理技术的发展突破像素分辨率的限制
- 批准号:
18300056 - 财政年份:2006
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$ 2.3万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
High-speed subpixel image sensing technique and its applications
高速亚像素图像传感技术及其应用
- 批准号:
15300050 - 财政年份:2003
- 资助金额:
$ 2.3万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
A Study of Massively Parallel Molecular Computing - Creating IntBrconnection'Free Computers -
大规模并行分子计算的研究 - 创建 IntBrconnectionFree 计算机 -
- 批准号:
13680385 - 财政年份:2001
- 资助金额:
$ 2.3万 - 项目类别:
Grant-in-Aid for Scientific Research (C)
Development of a Cluster Computing System for Evolutionary Synthesis of Hardware Algorithms
硬件算法进化综合集群计算系统的开发
- 批准号:
12558024 - 财政年份:2000
- 资助金额:
$ 2.3万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Development of a Real-Time Reconfigurable Signal Processor for Image Recognition
用于图像识别的实时可重构信号处理器的开发
- 批准号:
09558026 - 财政年份:1997
- 资助金额:
$ 2.3万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Development of Wavelength Detector ICs for Integrated Optical Multiplex Computing
用于集成光复用计算的波长检测器 IC 的开发
- 批准号:
06558036 - 财政年份:1994
- 资助金额:
$ 2.3万 - 项目类别:
Grant-in-Aid for Developmental Scientific Research (B)
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