DEVELOPMENT OF VACUUM MICRO DEVICES OPARATING AT LOW VOLTAGES WITH HIGH CURRENT DENSITY

低电压高电流密度真空微型器件的研制

基本信息

批准号：
07650400
负责人：
MURATA Kenji
金额：
$ 1.41万
依托单位：
OSAKA PREFECTURE UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1995
资助国家：
日本
起止时间：
1995 至 1996
项目状态：
已结题

项目摘要

It is important to develop a field emitter array (FEA) which works at low voltages with high current density. Both the gap between the emitter and the gate and the radius of the emitter curvature have to be made small in order to decrease the operating voltage. The emitter density has to be increased in order to obtain a high current density. The following experiments are performed in order to develop such novel FEAs.(i) Fabrication of lateral nickel FEAs.Since fine resist patterns have to be fabricated with high resolution, we use optical projection lithography with an oil immersion lens which has a high numerical aperture of 1.25. Nickel FEAs are fabricated by either lift-off technique or nickel plating by using the fabricated resist pattern. It is found that the FEA with a 0.3mum gap fabricated by the lift-off technique works from an operating voltage of 30V.The FEA with a 0.8mum gap fabricated by the nickel plating works from a voltage of 110V.(ii) Fabrication of high density vertical silicon emitters.Very fine resist gratings are fabricated with holographic lithography. A dots pattern can be obtained by applying a double exposure in the holographic lithography. The second exposure is done after the sample is rotated by 90ﾟ. The pattern of dots with a 0.2mum diameter and a 0.5mum period is obtained within the area of 2mm square. The density of dots is estimated as 4*10^6mm^<-2>. When a silicon substrate with the dots resist pattern is etched by CF_4 plasmas, a silicon emitter pattern with a high aspect ratio is obtained. However, the top of the emitter is not sharp. We are planing to make sharp emitters by improving the plasma etching condition and/or applying the oxidation for sharpening.In a further study we think it will be possible to improve the fabrication process of lateral nickel FEAs which work at lower voltages and establish the fabrication process of vertical silicon FEAs.

开发一种在低电压和高电流密度下工作的场发射器阵列（FEA）非常重要，为了降低工作电压，发射极和栅极之间的间隙以及发射极曲率半径都必须变小。为了获得高电流密度，必须增加发射极密度。为了开发这种新颖的FEA，进行了以下实验。(i)横向镍FEA的制造。因为必须用精细的抗蚀剂图案来制造。为了获得高分辨率，我们使用具有 1.25 高数值孔径的油浸透镜的光学投影光刻技术，通过使用所制造的抗蚀剂图案通过剥离技术或镀镍来制造镍 FEA。采用剥离技术制造的 0.3μm 间隙的工作电压为 30V。采用镀镍技术制造的 0.8μm 间隙的 FEA 的工作电压为电压为110V。(ii)高密度垂直硅发射器的制造。通过在全息光刻中应用两次曝光可以获得非常精细的抗蚀剂光栅。在样品之后进行第二次曝光。旋转90ﾟ，在2mm见方的面积内得到直径为0.2mum、周期为0.5mum的点的图案。点的密度估计为4×10^6mm^-2>。当用CF_4等离子体蚀刻具有点抗蚀剂图案的硅衬底时，获得具有高纵横比的硅发射极图案。我们计划通过改善等离子体蚀刻条件和/或应用氧化来锐化来制造锋利的发射器。在进一步的研究中，我们认为可以改进发射器的制造工艺。横向镍有限元分析在较低电压下工作并建立了垂直硅有限元分析的制造工艺。