DEVELOPMENT OF VACUUM MICRO DEVICES OPARATING AT LOW VOLTAGES WITH HIGH CURRENT DENSITY

低电压高电流密度真空微型器件的研制

基本信息

批准号：
07650400
负责人：
MURATA Kenji
金额：
$ 1.41万
依托单位：
OSAKA PREFECTURE UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1995
资助国家：
日本
起止时间：
1995 至 1996
项目状态：
已结题

项目摘要

It is important to develop a field emitter array (FEA) which works at low voltages with high current density. Both the gap between the emitter and the gate and the radius of the emitter curvature have to be made small in order to decrease the operating voltage. The emitter density has to be increased in order to obtain a high current density. The following experiments are performed in order to develop such novel FEAs.(i) Fabrication of lateral nickel FEAs.Since fine resist patterns have to be fabricated with high resolution, we use optical projection lithography with an oil immersion lens which has a high numerical aperture of 1.25. Nickel FEAs are fabricated by either lift-off technique or nickel plating by using the fabricated resist pattern. It is found that the FEA with a 0.3mum gap fabricated by the lift-off technique works from an operating voltage of 30V.The FEA with a 0.8mum gap fabricated by the nickel plating works from a voltage of 110V.(ii) Fabrication of high density vertical silicon emitters.Very fine resist gratings are fabricated with holographic lithography. A dots pattern can be obtained by applying a double exposure in the holographic lithography. The second exposure is done after the sample is rotated by 90ﾟ. The pattern of dots with a 0.2mum diameter and a 0.5mum period is obtained within the area of 2mm square. The density of dots is estimated as 4*10^6mm^<-2>. When a silicon substrate with the dots resist pattern is etched by CF_4 plasmas, a silicon emitter pattern with a high aspect ratio is obtained. However, the top of the emitter is not sharp. We are planing to make sharp emitters by improving the plasma etching condition and/or applying the oxidation for sharpening.In a further study we think it will be possible to improve the fabrication process of lateral nickel FEAs which work at lower voltages and establish the fabrication process of vertical silicon FEAs.

重要的是开发一个场发射器阵列（FEA），该磁场阵列（FEA）以高电流密度的低压工作。必须使发射极和栅极曲率的半径之间的缝隙缩小，以降低工作电压。必须增加发射极密度才能获得高电流密度。进行以下实验以开发这种新颖的雌性。（i）制造侧镍夫妇。由于必须使用高分辨率来制造良好的耐药性模式，我们使用具有浸入油的光刻镜，其高数值孔径为1.25。通过使用制造的抵抗图案，通过提升技术或镍板制造镍雌性。发现通过升降技术制造的0.3mum间隙的FEA可用于30V的工作电压。FEA的FEA具有由110V电压的镍电镀工程制造的0.8MUM间隙。可以通过在全息岩性摄影中进行双重暴露来获得点模式。在将样品旋转90 ﾟ旋转后进行第二次暴露。在2mm平方的区域内获得了直径为0.2MUM和0.5MUM周期的点的图案。点的密度估计为4*10^6mm^<-2>。当CF_4等离子体蚀刻具有DOTS模式的硅底物时，获得了具有高纵横比的硅发射极图。但是，发射极的顶部并不锋利。我们计划通过改善等离子体蚀刻条件和/或施用氧化以进行锐化来制作尖锐的发射器。在进一步的研究中，我们认为可以改善在较低电压下工作并建立垂直硅养父的制造过程的侧向镍孕期的制造过程。