Development of a Real-Time Reconfigurable Signal Processor for Image Recognition

用于图像识别的实时可重构信号处理器的开发

基本信息

批准号：
09558026
负责人：
AOKI Takafumi
金额：
$ 3.2万
依托单位：
TOHOKU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1999
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09558026/
关键词：
Hardware Algorithms Computer Arithmetic Integrated Circuits Datapath Redundant Number Systems Digital Signal Processors Image Recognition Digital Signal Processing 算術演算回路 VLSI 信号処理

项目摘要

Recently, we have proposed a DSP-oriented image recognition algorithm based on Phase-Only Correlation (POC). For applying the proposed algorithm to practical image recognition tasks, high-speed computation of real/complex-mixed data is essential. In this research project, we investigated a signal processor architecture for POC-based image recognition. Non-binary data representations, such as redundant complex number systems and high-radix redundant number systems, are employed to perform fast real/complex-mixed computation. We have developed the key components for the signal processor as listed below:1. A real/complex reconfigurable arithmetic unit, that can change its structure for three different operation modes, has been proposed and fabricated in 0.5um CMOS. The three modes realize complex-number multiplication, double-length real-number multiplication, and real-number multiply-add operation. The reconfiguration overhead is significantly low, which corresponds to only 8.9% increase … More of transistor count.2. A redundant complex multiplier has been proposed and fabricated in 0.5um CMOS. The chip area, interconnect delay and power consumption are reduced to 33.7%, 16.9% and 18.4%, respectively, compared with a complex-number multiplier designed by a standard logic synthesis tool.3. A configurable multiply-adder based on SW (Signed-Weight) arithmetic has been proposed and fabricated in 0.35um CMOS. The fabricated chip can perform FIR filtering with high sampling-rate around 10MHz-100MHz.4. A parallel divider and a CORDIC vector rotator for 3D image processing have been proposed and fabricated. The use of high-radix redundant number systems makes possible low-latency implementations of iterative arithmetic operations.In addition to the above results, various applications of POC-based image recognition have been investigated. We developed a 3D (stereo) vision system using hierarchical phase-only matching, and clarified architectural requirements toward the implementation of a new signal processor for 3D measurement and object recognition. Less

最近，我们提出了一种基于纯相位相关（POC）的面向 DSP 的图像识别算法，为了将所提出的算法应用于实际图像识别任务，真实/复杂混合数据的高速计算至关重要。在该项目中，我们研究了一种用于基于 POC 的图像识别的信号处理器架构，例如冗余复数系统和高基数冗余数系统，用于执行快速实数/复数混合计算。我们开发了信号处理器的关键组件，如下所示： 1．提出并在 0.5um CMOS 中制造了一种实数/复数可重构运算单元，它可以改变其结构以适应三种不同的操作模式。数乘法、双长度实数乘法和实数乘加运算的重新配置开销非常低，仅相当于晶体管数量的 8.9% 增加。2. 冗余复数。与标准逻辑综合工具设计的复数乘法器相比，该乘法器已被提出并采用 0.5um CMOS 制造，芯片面积、互连延迟和功耗分别降低至 33.7%、16.9% 和 18.4%。提出了一种基于SW（有符号权重）算法的可配置乘法加法器，并在0.35um CMOS 上制造了该芯片。 10MHz-100MHz 左右高采样率的 FIR 滤波已被提出并制造用于 3D 图像处理的并行除法器和 CORDIC 矢量旋转器。高基数冗余数系统的使用使得迭代算法的低延迟实现成为可能。除了上述结果之外，我们还研究了基于 POC 的图像识别的各种应用，并使用分层纯相位匹配开发了 3D（立体）视觉系统。明确了实施用于 3D 测量和物体识别的新信号处理器的架构要求。