Computer-Aided Design for High-Performance Large-Scale Integrated Circuits

高性能大规模集成电路的计算机辅助设计

• 批准号: RGPIN-2015-03759
• 负责人: Najm, Farid
• 金额: $ 2.7万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2018
• 资助国家: 加拿大
• 起止时间: 2018-01-01 至 2019-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=660615
• 关键词: Computer; Aided; Design; Performance; Large

In order to enable the design of future advanced large-scale integrated circuits (ICs), we are developing computer-aided design (CAD) tools and techniques to address a number of challenges relating to the verification, optimization, and design of the chip power distribution network (PDN), also simply referred to as the power grid. With increased power dissipation and reduced supply voltage, large microprocessors today draw over 150 Amperes from the external supply! These levels of current are unprecedented in microelectronics, and are a key challenge for design. Apart from the design issues of delivering well-regulated low voltages at these extremes of current, a key problem for designers is to make sure that the increased voltage drop and/or rise (due to IR-drop and/or Ldi/dt drop) in the chip PDN do not lead to circuit delay errors and functional failures. However, checking the grid node voltages is very time-consuming and expensive, so that it is often incompletely done, or not done at all. We have worked for the last decade on power grid verification, but we now propose to embark on an innovative new research direction to develop new techniques for enabling verification, design and optimization of the power grid. This new direction involves solving the inverse of the traditional verification problem: instead of asking users to provide the circuit currents and reporting to them whether or not the grid is safe, we simply tell them what ranges or combinations of circuit currents would be guaranteed to maintain grid safety. There are many advantages for this approach, such as large improvements in the speed of verification, as well as valuable information for design placement and floorplanning regarding the locations on the chip where high power blocks may be placed.**

为了实现未来先进大规模集成电路（IC）的设计，我们正在开发计算机辅助设计（CAD）工具和技术，以解决与芯片电源验证、优化和设计相关的一系列挑战配电网（PDN），也简称为电网。随着功耗的增加和电源电压的降低，当今的大型微处理器从外部电源汲取的电流超过 150 安培！这些电流水平在微电子领域是前所未有的，并且是设计的关键挑战。 除了在这些极端电流下提供良好调节的低电压的设计问题之外，设计人员面临的一个关键问题是确保增加的压降和/或上升（由于 IR 压降和/或 Ldi/dt 压降）芯片内的PDN不会导致电路延迟错误和功能故障。然而，检查电网节点电压非常耗时且昂贵，因此常常不完全完成或根本没有完成。过去十年我们一直致力于电网验证，但现在我们建议着手一个创新的新研究方向，开发新技术来实现电网的验证、设计和优化。这个新方向涉及解决传统验证问题的逆过程：我们不再要求用户提供电路电流并向他们报告电网是否安全，而是简单地告诉他们电路电流的范围或组合可以保证维持在什么范围或组合电网安全。这种方法有很多优点，例如验证速度的大幅提高，以及有关芯片上可能放置高功率块的位置的设计布局和布局规划的宝贵信息。 **