Development of New FET-Type Ferroelectric Memory with an Intermediate Electrode

具有中间电极的新型 FET 型铁电存储器的开发

基本信息

批准号：
15560293
负责人：
HORITA Susumu
金额：
$ 2.37万
依托单位：
Japan Advanced Institute of Science and Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2004
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-15560293/
关键词：
Ferroelectric Memory Silicon PZT Ferroelectric

项目摘要

1.Reduction of Reading Voltage V_RWe used different electrode materials for the top and bottom electrodes of the ferroelectric PZT film in order to reduce e V_R. The bottom electrode is an intermediate electrode of Ir and the top electrodes are IrO_2, RuO_2 and PtO_x. The hysteresis loop of the PZT film was shifted toward positive electric field (E) in order of Ir-O_2, RuO_2 and PtO_x, which means that an inner E exists in the PZT films. Although this E reduces V_R, it assists the change of the remanent polarization, i.e., memory state, which is unfavorable for non-volatile memory.2.Increase of Reading NumberThis memory has one problem that the memory state is changed by reading because the remanent polarization sate is changed due to the leakage current through the off-state writing FET for reading. For this problem, we proposed one method that the electric intermediate point is connected to the drain region of the reading FET. By using this, the leakage current is reduced so that the reading number is increased by about one order than the conventional connection.3.Fabrication of the Integrated circuitsWe confirmed the principle operation of the integrated circuits of our new memory on an Si wafer under the conditions that the writing voltage was 5 V and the VR was 7 V. However, the difference on output voltage between two memory states was only 15 mV and very small. This is because the thickness of the YSZ film can be never thinned and the dielectric constant of the PZT film is large. Also, the gate leakage current flows largely. For these problems, we suggest one solution to use not only SiO_2 film with good interface property to Si instead of YSZ and but also ferroelectric materials with lower dielectric constant.

1.读取电压V_RWE的读数使用不同的电极材料，用于铁电PZT膜的顶部和底部电极，以减少E V_R。底部电极是IR的中间电极，顶部电极为IRO_2，RUO_2和PTO_X。 PZT膜的磁滞回路按IR-O_2，RUO_2和PTO_X顺序转移到正电场（E），这意味着内部E存在于PZT膜中。尽管此e减少了v_r，但它有助于变化remanent两极分化，即记忆状态，这不利于非易失性记忆。2。读取号码的记忆存在一个问题，即通过阅读来改变内存状态，因为Remanent是Remanent偏振现象因泄漏电流而改变了，因此通过州外写作FET进行阅读。对于这个问题，我们提出了一种方法，即电中间点连接到读取FET的排水区域。通过使用此功能，泄漏电流减少了，因此比常规连接的读数增加了约一个顺序。3。综合电路的制作确认了我们新内存的集成电路的原理操作写入电压为5 V，VR为7V。但是，两个存储器状态之间的输出电压的差异仅为15 mV且非常小。这是因为YSZ膜的厚度永远不会被稀释，并且PZT膜的介电常数很大。同样，门泄漏电流大大流动。对于这些问题，我们建议一种解决方案，不仅使用具有良好接口属性的SIO_2膜，而不是YSZ，还使用具有较低介电常数的铁电材料。