Highly Parallel Network Processor Based on Self Timed Pipeline Circuit

基于自定时流水线电路的高度并行网络处理器

基本信息

批准号：
15500056
负责人：
IWATA Makoto
金额：
$ 1.98万
依托单位：
Kochi University of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2004
项目状态：
已结题

项目摘要

The objectives of this research project is to establish a flexible architecture of highly integrated network processor drip by exhaustively utilizing the self-timed pipeline as one of low-power, easily designed and high performance circuits. A part of the project has been conducted through developing and evaluating a newly designed LSI. The following basic research results have been obtained in this Project by applying the proposed architecture to the class based QoS control function like Diffserv and the high-level packet filtering such as that of firewall and intruder detection systam (IOS).1 Self-Timed priocity queueing mechanismWe proposed a self-timed priority queueing mechanism in which every pair of stage of a folded pipeline has a bypass stage to minimize queueing delay time. We observed that the test chip fabricated by 0.18 um CMOS process could achieve around 100 M IP packets/s with 8 different classes.2 Data-driven implementation of high-speed packet filteringWe proposed two data-driven implementations one is a static filtering of layer 4 packet header and the other one is a signature matching for payload inspection. Our evaluation results showed that 4 M packets/s for the static filtering and 0.1 M packets/s for the signature matching could be achieved on only one date-driven processor. Additional circuit cost of some dedicated instructions for the static filtering was evaluated by implementing a self-timed data-driven processor on FPGA. The result indicated that only 6 % increase of gates was enough to realize the proposed architecture.3 Performance estimation model of the self-timed pipelined systemsWe formulated a macro flow model by which the behavior of ever packet flowing in a self-timed pipeline can be modeled simply. Using this model, we can reduce simulation time of the self-timed pipelined systems in half with reasonable accuracy in comparison to the existing naive model.

本研究项目的目标是充分利用自定时流水线作为低功耗、易于设计和高性能电路之一，建立一种灵活的高度集成网络处理器点滴架构。该项目的一部分是通过开发和评估新设计的 LSI 来进行的。通过将所提出的体系结构应用于基于类别的 QoS 控制功能（如 Diffserv）以及高级数据包过滤（如防火墙和入侵者检测系统（IOS）的高级数据包过滤），本项目获得了以下基础研究成果。 1 自定时优先级排队机制我们提出了一种自定时优先级排队机制，其中折叠管道的每对阶段都有一个旁路阶段，以最小化排队延迟时间。我们观察到，采用 0.18 um CMOS 工艺制造的测试芯片可以实现约 100 M IP 数据包/秒，具有 8 个不同的类别。 2 高速数据包过滤的数据驱动实现我们提出了两种数据驱动的实现，一种是层的静态过滤4 个数据包头，另一个是用于有效负载检查的签名匹配。我们的评估结果表明，仅在一台数据驱动处理器上即可实现 4 M 数据包/秒的静态过滤速度和 0.1 M 数据包/秒的签名匹配速度。通过在 FPGA 上实现自定时数据驱动处理器来评估一些静态滤波专用指令的额外电路成本。结果表明，仅增加 6% 的门就足以实现所提出的体系结构。 3 自定时流水线系统的性能估计模型我们制定了一个宏观流模型，通过该模型可以描述自定时流水线中每个数据包流动的行为。建模简单。与现有的朴素模型相比，使用该模型，我们可以将自定时管道系统的仿真时间减少一半，并且具有合理的精度。

项目成果

期刊论文数量（45）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

A macroscopic behavior model for self-timed pipeline systems

DOI：
10.1109/pads.2003.1207429
发表时间：
2003-06
期刊：
Seventeenth Workshop on Parallel and Distributed Simulation, 2003. (PADS 2003). Proceedings.
影响因子：
0
作者：
Shuji Sannomiya;Y. Omori;M. Iwata
通讯作者：
Shuji Sannomiya;Y. Omori;M. Iwata

Super-Pipelined Implementation of IP Packet Classification

IP 数据包分类的超级流水线实现

DOI：
发表时间：
2004
期刊：
Journal of Intelligent Automation and Soft Computing 10・2
影响因子：
0
作者：
Tomoyuki Ohta;Munehiko Fujimoto;Ryotaro Oda;Yoshiaki Kakuda;Y.Shi et al.;Daichi MORIKAWA
通讯作者：
Daichi MORIKAWA

林秀樹: "異種混合ネットワークにおける自律型フロー分散制御方式"情報処理学会論文誌. 45・2. 426-437 (2004)

Hideki Hayashi：“异构网络中的自主流分布式控制方法”日本信息处理学会会刊45・2（2004）。