A Study on How Implementing Microprocessors Exploiting Instruction Level Parallelism

关于如何实现微处理器利用指令级并行性的研究

• 批准号: 13558030
• 负责人: SATO Toshinori
• 金额: $ 4.42万
• 依托单位: Kyushu Institute of Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2001
• 资助国家: 日本
• 起止时间: 2001 至 2003
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-13558030/
• 关键词: ILP; Processors; Reissue; Fault Tolerance; Speculation; Power; Critical Path; LSI; プロセッサ; エネルギー; 信頼性; スーパースカラ; 半導体技術; 命令レベル並列処理

Power consumption is a major concern in embedded microprocessors design.Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power..Regarding the effect of sustaining throughput on power and performance, it is found that pipelined functional units are better in energy reduction as well as in performance than non-pipelined units even if the increase in hardware due to extra latches are considered. We also evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is currently not a good design choice for energy efficiency.

功耗是嵌入式微处理器设计中的一个主要问题。降低功耗也是通用微处理器的一个关键设计目标。由于它们需要高性能和低功耗，因此以性能为代价来降低功耗是不能接受的。有许多设备级技术可以在保持性能的同时降低功耗。他们选择非关键路径作为低功耗设计的候选路径，而面向性能的设计仅用于速度关键路径。同样的理念也可以应用于架构级别的设计。我们评估了一种技术，该技术利用有关指令关键性的动态信息来降低功耗。关于维持吞吐量对功耗和性能的影响，我们发现流水线功能单元在能耗和性能方面都比非流水线功能单元更好。即使考虑到由于额外的锁存器而导致的硬件增加，流水线单元也是如此。我们还评估了基于指令关键性的集群微架构的指令引导策略，发现它目前并不是能源效率的良好设计选择。

项目成果

Toshinori Sato, Itsujiro Arita: "Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse"Proc. 7^<th> International Euro-Par Conference. 428-438 (2001)

Toshinori Sato、Itsujiro Arita：“通过可变延迟管道和指令重用减少执行延迟”Proc。

Akihiro Chiyonobu, Toshinori Sato, Itsujiro Arita: "An Evaluation of Critical Path Predictors for Low Power Processor Architecture"IEICE Transactions on, Electronics. vol.J86-C, no.8 August. (2003)

Akihiro Chiyonobu、Toshinori Sato、Itsujiro Arita：“低功耗处理器架构关键路径预测器的评估”IEICE Transactions，电子学。

佐藤寿倫, 有田五次郎: "可変レイテンシパイプライン技術と演算結果再利用技術の併用による演算レイテンシ削減"電子情報通信学会論文誌D-I. J85-D-I・12. 1103-1113 (2002)

Toshihiro Sato、Gojiro Arita：“通过结合可变延迟管道技术和计算结果重用技术来减少计算延迟”IEICE Transactions D-I·1103-1113（2002）。

Toshinori Sato: "A Transparent Transient Faults Tolerance Mechanism for Superscalar Processors"IEICE Transactions on Information and Systems. vol.E86-D, no.12 December. (2003)

Toshinori Sato：“超标量处理器的透明瞬态容错机制”IEICE Transactions on Information and Systems。

佐藤寿倫, 有田五次郎: "過渡故障に対するマイクロプロセッサ向けフォールトトレランス技術の提案"並列処理シンポジウム予稿集. 335-342 (2001)

Hisanori Sato、Gojiro Arita：“微处理器针对瞬态故障的容错技术提案”并行处理研讨会论文集 335-342 (2001)。