Collaborative Research: SHF: Medium: Tiny Chiplets for Big AI: A Reconfigurable-On-Package System

合作研究：SHF：中：用于大人工智能的微型芯片：可重新配置的封装系统

• 批准号: 2403408
• 负责人: Yu Cao
• 金额: $ 80万
• 依托单位: University of Minnesota-Twin Cities
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2024
• 资助国家: 美国
• 起止时间: 2024-07-01 至 2028-06-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2403408&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; Medium; Tiny

As monolithic chips reach their technological and practical limits, the integration of chiplets is emerging as the primary mechanism to continuously scale up processor performance, improve power efficiency, enhance IP reuse at low cost, and expedite time-to-market. This new concept of composable chiplets is particularly appealing to the artificial intelligence (AI) sector, which is in a pressing need to deliver computing chips to support increasingly complex and diverse cognitive algorithms. This project aims to pioneer such a computing system, including new architectural and design automation tools, for massive AI workloads. The envisioned system will benefit various scenarios, ranging from high-performance computing applications to mobile and edge devices. This project also addresses the skill shortage in the semiconductor area, a crucial aspect for reshoring the semiconductor industry. It involves training students in the areas of heterogeneous system design, AI architectures, and design automation. The investigators plan to improve the knowledge base through new curriculum development, engaging undergraduate students in research through Research Experiences for Undergraduates (REU) supplement, and participating in outreach programs customized for K-12 students. In addition, this project will advocate web-based knowledge dissemination including releasing software codes and novel designs. Several workshops and tutorials promoting chiplet-based co-design have been organized by the investigators and will be continued.Distinguished from current practice of 2.5D/3D heterogeneous integration (HI), this project aims to transform the architecture of chiplet-based design through three unique perspectives: Miniaturization to reduce the chiplet size to the minimum (tiny chiplets) for high composability, guided by AI computing cores; Very-large-scale integration to integrate thousands of tiny chiplets to scale up computing power and diversity for big AI applications, offering unprecedented flexibility and efficiency for AI algorithm and system designers; and Reconfiguration on the package to enable adaptation to varying workloads and address thermal and reliability concerns in 2.5D/3D packaging. These innovations will push the limits of architecture and physical design, addressing challenges related to chiplet definition, interconnection, power and thermal integrity, and workload mapping. The objective is to create a suite of design automation tools, streamlining the complete design process of reconfigurable chiplet-based systems for big AI computing.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

随着单片芯片达到其技术和实际极限，小芯片的集成正在成为不断扩展处理器性能、提高能效、以低成本增强 IP 重用以及加快上市时间的主要机制。这种可组合小芯片的新概念对人工智能 (AI) 领域特别有吸引力，该领域迫切需要提供计算芯片来支持日益复杂和多样化的认知算法。该项目旨在开创这样一个计算系统，包括新的架构和设计自动化工具，用于大规模人工智能工作负载。设想的系统将有利于各种场景，从高性能计算应用程序到移动和边缘设备。该项目还解决了半导体领域的技能短缺问题，这是半导体行业回流的一个关键方面。它涉及对异构系统设计、人工智能架构和设计自动化领域的学生进行培训。研究人员计划通过新课程开发、通过本科生研究经验 (REU) 补充让本科生参与研究以及参与为 K-12 学生定制的外展计划来改善知识库。此外，该项目将倡导基于网络的知识传播，包括发布软件代码和新颖的设计。研究人员已经组织了多个促进基于chiplet的协同设计的研讨会和教程，并将继续进行。与当前2.5D/3D异构集成（HI）的实践不同，该项目旨在通过以下方式改变基于chiplet的设计架构：三个独特的视角： 小型化，将小芯片尺寸降至最小（微型小芯片），以实现高可组合性，以人工智能计算核心为指导；超大规模集成，集成数千个微小芯片，以扩展大型人工智能应用的计算能力和多样性，为人工智能算法和系统设计人员提供前所未有的灵活性和效率；对封装进行重新配置，以适应不同的工作负载并解决 2.5D/3D 封装中的散热和可靠性问题。这些创新将突破架构和物理设计的极限，解决与小芯片定义、互连、电源和热完整性以及工作负载映射相关的挑战。目标是创建一套设计自动化工具，简化用于大人工智能计算的可重构小芯片系统的完整设计流程。该奖项反映了 NSF 的法定使命，并通过利用基金会的智力优势和更广泛的评估进行评估，认为值得支持。影响审查标准。