CAREER: Next Generation of High-Level Synthesis for Agile Architectural Design (ArchHLS)

职业:下一代敏捷架构设计高级综合 (ArchHLS)

基本信息

  • 批准号:
    2338365
  • 负责人:
  • 金额:
    $ 56万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Continuing Grant
  • 财政年份:
    2024
  • 资助国家:
    美国
  • 起止时间:
    2024-06-01 至 2029-05-31
  • 项目状态:
    未结题

项目摘要

In the landscape of computing, the demand for innovative hardware architectures is ever-growing, driving advancements in computer architecture. However, the conventional Register Transfer Level (RTL) design approach is time-consuming and labor-intensive. This project aims to facilitate the broader adoption of High-Level Synthesis (HLS) tools to significantly reduce design time, particularly for general architectural design. HLS tools enable higher-level programming and automatic synthesis, yet their application in comprehensive computer architecture studies remains limited. The significance of this project lies in promoting agile hardware development by fundamentally innovating HLS tools, overcoming the productivity challenges at the register transfer level, and unlocking the potential for more widespread application of HLS in diverse computing domains. The developed tool chain will be publicly available and exposed to more users by organizing tutorials, workshops, and demo events. The research will be integrated into education programs with activities on research training for undergraduate and master students, including online students, recruitment and retention of students from underrepresented groups, curriculum development, and innovative international design competitions co-hosted with industry.This project aims to revolutionize High-Level Synthesis (HLS) tools by introducing a next-generation tool, ArchHLS, addressing two major research challenges. First, HLS tools are superior in synthesizing a specific algorithm into hardware but have limited capability for general domain-specific architecture designs. Second, it is challenging to design general architectures with compatible compilers and to automatically improve the underlying architecture for evolving workloads. To address these challenges, ArchHLS facilitates agile hardware development by making three key innovations. First, ArchHLS decouples architectural design and workload mapping, allowing flexible architecture extraction and customized control flow. Second, ArchHLS automates architecture evolution to adapt to fast-changing algorithms via automated workload compilation, mapping, and computation pattern matching. Third, ArchHLS enables comprehensive and accurate performance profiling for designs to provide feedback for architecture evolution. Beyond advancing Electronic Design Automation (EDA) tooling, this research has broader societal implications, aligning with the grand vision of sustainability for computing and computing for sustainability, such as climate modeling and scientific computing. The public availability of the toolchain fosters research dissemination, educational integration, and inclusivity efforts, aiming to benefit diverse communities and promote efficient algorithm/architecture co-design.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
在计算领域,对创新硬件架构的需求不断增长,推动了计算机架构的进步。然而,传统的寄存器传输级(RTL)设计方法既耗时又费力。该项目旨在促进高级综合(HLS)工具的更广泛采用,以显着缩短设计时间,特别是对于通用架构设计。 HLS 工具可以实现更高级别的编程和自动综合,但它们在综合计算机体系结构研究中的应用仍然有限。该项目的意义在于通过从根本上创新HLS工具来促进敏捷硬件开发,克服寄存器传输层面的生产力挑战,并释放HLS在不同计算领域更广泛应用的潜力。开发的工具链将公开发布,并通过组织教程、研讨会和演示活动向更多用户展示。该研究将融入教育计划中,为本科生和硕士生提供研究培训活动,包括在线学生、招收和留住弱势群体学生、课程开发以及与业界共同举办的创新国际设计竞赛。该项目旨在通过引入下一代工具 ArchHLS,彻底改变了高级综合 (HLS) 工具,解决了两大研究挑战。首先,HLS 工具在将特定算法综合到硬件中方面表现出色,但对于一般特定领域架构设计的能力有限。其次,设计具有兼容编译器的通用架构并自动改进底层架构以适应不断变化的工作负载是具有挑战性的。为了应对这些挑战,ArchHLS 通过三项关键创新来促进敏捷硬件开发。首先,ArchHLS 将架构设计和工作负载映射解耦,允许灵活的架构提取和定制控制流。其次,ArchHLS 通过自动工作负载编译、映射和计算模式匹配来自动化架构演进,以适应快速变化的算法。第三,ArchHLS 能够为设计提供全面、准确的性能分析,为架构演进提供反馈。除了先进的电子设计自动化 (EDA) 工具之外,这项研究还具有更广泛的社会影响,符合计算可持续发展和计算可持续发展的宏伟愿景,例如气候建模和科学计算。该工具链的公开可用性促进了研究传播、教育整合和包容性努力,旨在造福多元化社区并促进高效的算法/架构协同设计。该奖项反映了 NSF 的法定使命,并通过使用基金会的评估进行评估,认为值得支持。智力价值和更广泛的影响审查标准。

项目成果

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Cong Hao其他文献

Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip
针对特定应用片上网络的节能分区和集群生成设计
A Unified Scheduling Approach for Power and Resource Optimization with Multiple V-dd or/and V-th in High Level Synthesis
高级综合中使用多个 V-dd 或/和 V-th 进行功率和资源优化的统一调度方法
  • DOI:
  • 发表时间:
    2017
  • 期刊:
  • 影响因子:
    2.9
  • 作者:
    Cong Hao; Nan Wang; Takeshi Yoshimura
  • 通讯作者:
    Takeshi Yoshimura
EACH: An Energy-Efficient High-Level Synthesis Framework for Approximate Computing
EACH:一种用于近似计算的节能高级综合框架
  • DOI:
  • 发表时间:
    2016
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Cong Hao;Takeshi Yoshimura
  • 通讯作者:
    Takeshi Yoshimura
Simultaneous Scheduling and Binding for Resource Usage and Interconnect Complexity Reduction in High-Level Synthesis
高级综合中资源使用的同时调度和绑定以及互连复杂性降低
  • DOI:
  • 发表时间:
    2015
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Cong Hao; Jian;Takeshi Yoshimura
  • 通讯作者:
    Takeshi Yoshimura
Scenario Generation for Wind Power Using Generative Adversarial Networks
使用生成对抗网络生成风力发电场景
  • DOI:
    10.1088/1742-6596/2320/1/012019
  • 发表时间:
    2022-08-01
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Tiancheng Shi;De Gejirifu;Cong Hao;Wenzhang Guo;Zhong Yalin;Qian Long
  • 通讯作者:
    Qian Long

Cong Hao的其他文献

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{{ truncateString('Cong Hao', 18)}}的其他基金

CSR: Small: Multi-FPGA System for Real-time Fraud Detection with Large-scale Dynamic Graphs
CSR:小型:利用大规模动态图进行实时欺诈检测的多 FPGA 系统
  • 批准号:
    2317251
  • 财政年份:
    2024
  • 资助金额:
    $ 56万
  • 项目类别:
    Standard Grant
Machine Learning-assisted Modeling and Design of Approximate Computing with Generalizability and Interpretability
具有通用性和可解释性的机器学习辅助建模和近似计算设计
  • 批准号:
    2202329
  • 财政年份:
    2022
  • 资助金额:
    $ 56万
  • 项目类别:
    Standard Grant

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Next Generation Majorana Nanowire Hybrids
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  • 批准年份:
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  • 资助金额:
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SoLoMo情形下“下一个最佳购物建议”(NBO)对消费者决策的影响机制研究
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    71302093
  • 批准年份:
    2013
  • 资助金额:
    22.0 万元
  • 项目类别:
    青年科学基金项目

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