Collaborative Research: An Effective and Efficient Low-Cost Alternate to Cell Aware Test Generation for Cell Internal Defects

协作研究：针对电池内部缺陷的电池感知测试生成有效且高效的低成本替代方案

• 批准号: 2331003
• 负责人: Adit Singh
• 金额: $ 30万
• 依托单位: Auburn University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2331003&HistoricalAwards=false
• 关键词: Collaborative; Research; Effective; Efficient; Low

Society’s growing reliance on intelligent electronic systems risks significant disruption and loss from integrated circuit failure. Mitigating this threat requires building electronic systems that have been extensively tested to ensure that they are fully functional and defect-free. Modern integrated circuits contain billions of transistors that makes a complete exhaustive test of circuit functionality impractical and infeasible. Such tests are generated in practice, by considering the impact of likely manufacturing defects such as shorts and opens at various circuit locations, and developing a set of input test patterns whose correct binary output is altered by the existence of any targeted fault, identifying a bad integrated circuit. However, it is not practical to model and target all possible malfunctions in a large circuit, especially those that employ deeply scaled technologies, low supply voltages and high clock speeds. As a consequence, some faulty circuits inevitably escape post-manufacture testing because of incomplete test coverage and cause integrated circuit failure when deployed in operation. The goal of this research is to develop better and significantly more cost-effective test methods for state-of-the-art integrated circuits that can significantly impact the affordability and reliability of future computing systems that are increasingly pervasive in day-to-day societal applications and critical for national defense. The project will also help train new students in this strategic area, consistent with recent priorities for US leadership in semiconductor manufacturing. Traditional test methods for integrated circuits generate test inputs that explicitly detect faulty behavior only at the terminals of the standard cell building blocks and the interconnections between these cells. It is now widely known that detection of defective devices can be enhanced by considering defects within the cell circuitry as well. To do this, currently, faults are injected one at a time at likely defect locations in the cell layout, followed by exhaustive circuit simulation of all possible input patterns to obtain cell level tests. The generated tests are then delivered to cells embedded in logic circuitry using circuit-level test generation algorithms. This has major drawbacks. First, it is expensive to characterize the full range of resistive defects at every possible location in large cells using exhaustive circuit simulation. In practice, only ideal shorts and opens are simulated, leading to test escapes. Second, this does not consider the significant impact of a timing delay in one cell on the delays of other interconnected cells. Third, existing test generation techniques such as cell aware test, can increase test size and application time by greater than fivefold. To address these issues, this project seeks to develop a new testing methodology that avoids exhaustive simulation, but instead uses analytical reasoning to generate tests for cell internal defects. Algorithms based on this analytic approach can generate compact tests that cover defects spanning large resistance ranges without the need for repeated simulations. Additionally, the delay impact of a single defect that affects multiple cells can also be effectively captured, minimizing the escape of timing faults.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

社会对智能电子系统的日益依赖可能会因集成电路故障而造成重大破坏和损失。要减轻这种威胁，需要构建经过测试的电子系统，以确保其功能齐全且无缺陷。现代集成电路包含数十亿个广泛制造的晶体管。对电路功能进行全面详尽的测试是不切实际和不可行的，这种测试是在实践中通过考虑可能的制造缺陷（例如各个电路位置的短路和开路）的影响，并开发一组输入测试模式（其正确的二进制输出）来实现的。存在然而，对大型电路中所有可能的故障进行建模和定位是不切实际的，特别是那些采用深度扩展技术、低电源电压和高时钟速度的电路。由于测试覆盖范围不完整，有故障的电路不可避免地会逃避制造后测试，并在运行时导致集成电路故障。本研究的目标是为最先进的集成电路开发更好且更具成本效益的测试方法。这可能会严重影响负担能力该项目还将帮助培训这一战略领域的新学生，这与美国在半导体制造领域的领导地位最近的优先事项一致。集成电路的方法生成仅在标准单元构建块的端子和这些单元之间的互连处明确检测故障行为的测试输入。现在众所周知，可以通过将单元电路内的缺陷考虑为来增强对有缺陷器件的检测。为了做到这一点，目前，在单元布局中可能存在缺陷的位置一次注入一个故障，然后对单元级测试的所有可能输入模式进行详尽的电路模拟，然后使用电路级测试生成算法将生成的测试传递到嵌入逻辑电路中的单元。首先，使用详尽的电路模拟来表征大型电池中每个可能位置的全部电阻缺陷的成本很高，这会导致测试逃逸。不考虑重大影响第三，现有的测试生成技术（例如单元感知测试）可以将测试规模和应用时间增加五倍以上。为了解决这些问题，该项目寻求开发一种测试方法。新的测试方法避免了详尽的模拟，而是使用分析推理来生成电池内部缺陷的测试。基于这种分析方法的算法可以生成涵盖大电阻范围的缺陷的紧凑测试，而无需重复模拟。影响多个细胞的单一缺陷该奖项反映了 NSF 的法定使命，并通过使用基金会的智力优点和更广泛的影响审查标准进行评估，被认为值得支持。