Collaborative Research: DESC: Type II: REFRESH: Revisiting Expanding FPGA Real-estate for Environmentally Sustainability Heterogeneous-Systems

合作研究：DESC：类型 II：REFRESH：重新审视扩展 FPGA 空间以实现环境可持续性异构系统

• 批准号: 2324864
• 负责人: Peipei Zhou
• 金额: $ 150万
• 依托单位: University of Pittsburgh
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2027-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2324864&HistoricalAwards=false
• 关键词: Collaborative; Research; DESC; Type; II

Computing systems can exert substantial environmental impacts across their entire life cycles, encompassing manufacturing, usage, and end-of-life disposal. For example, manufacturing processes often require significant amounts of energy and produce substantial carbon emissions. When computers reach the end of their life, they become electronic waste (e-waste). E-waste, if not properly managed, can pose risks to human health and the environment due to the presence of hazardous materials. Mitigating these impacts is a significant challenge for sustainable computing. This project introduces innovative approaches to minimize the environmental impact of computing systems by recycling decommissioned chips, integrating them to extend their lifespans, and achieving near state-of-the-art performance with the newly integrated chips. The project will be carried out by a team of investigators from the University of Pittsburgh and the University of Notre Dame. The project's impacts are twofold: significantly reducing carbon emissions from manufacturing and mitigating environmental risks associated with e-waste by keeping these toxic, non-biodegradable devices out of landfills. This project is making valuable contributions to society through education and outreach activities designed to engage K-12 students with an interest in environmental science, biology, and artificial intelligence (AI).The primary goal of this project is to achieve sustainable computing by reusing recently retired field-programmable gate array (FPGA) chips to build REFRESH FPGA devices and employing 2.5-dimensional (2.5D) integration with an underlying interposer for interconnection. This approach aims to significantly reduce carbon emissions incurred from the fabrication process of new chips. The project consists of four research thrusts. Thrust 1 focuses on developing REFRESH FPGA architecture and design automation toolflow, tailored to address the challenge of targeting hardware designs onto non-monolithic FPGAs. Thrust 2 investigates REFRESH FPGA hardware analysis and prototyping through a design automation framework capable of automatically selecting the optimal design configuration including inter-chip connection topology, connection bandwidth, and the selection of FPGA chips based on their aging condition. Thrust 3 is dedicated to developing a system-in-a-package sustainability analysis, validation, and optimization process, aiming to accurately model and assess the environmental impacts stemming from the 2.5D integrated REFRESH FPGAs including fabrication, integration, and packaging. Thrust 4 extensively explores the most effective methodologies for accelerating a wide range of applications from machine learning to genomics.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

计算系统可以在其整个生命周期中产生重大的环境影响，包括制造、使用和报废处理。例如，制造过程通常需要大量能源并产生大量碳排放。当计算机达到其使用寿命时，它们就成为电子垃圾（e-waste）。电子废物如果管理不当，可能会因有害物质的存在而对人类健康和环境构成风险。减轻这些影响是可持续计算面临的重大挑战。该项目引入了创新方法，通过回收退役芯片、集成它们以延长其使用寿命，以及利用新集成的芯片实现近乎最先进的性能，最大限度地减少计算系统对环境的影响。该项目将由匹兹堡大学和圣母大学的研究小组进行。该项目的影响是双重的：显着减少制造过程中的碳排放，并通过将这些有毒的、不可生物降解的设备排除在垃圾填埋场来减轻与电子废物相关的环境风险。该项目通过旨在吸引对环境科学、生物学和人工智能 (AI) 感兴趣的 K-12 学生的教育和外展活动为社会做出了宝贵贡献。该项目的主要目标是通过重复使用最近的计算来实现可持续计算使用退役的现场可编程门阵列 (FPGA) 芯片来构建 REFRESH FPGA 器件，并采用 2.5 维 (2.5D) 与底层中介层集成进行互连。这种方法旨在显着减少新芯片制造过程中产生的碳排放。该项目由四个研究重点组成。 Thrust 1 专注于开发 REFRESH FPGA 架构和设计自动化工具流程，旨在解决将硬件设计应用于非单片 FPGA 的挑战。 Thrust 2 通过设计自动化框架研究 REFRESH FPGA 硬件分析和原型设计，该框架能够自动选择最佳设计配置，包括芯片间连接拓扑、连接带宽以及根据 FPGA 芯片的老化情况进行选择。 Thrust 3 致力于开发系统级封装可持续性分析、验证和优化流程，旨在准确建模和评估 2.5D 集成 REFRESH FPGA 所产生的环境影响，包括制造、集成和封装。 Thrust 4 广泛探索了最有效的方法，以加速从机器学习到基因组学的广泛应用。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP

目的：在异构可重构计算平台 Versal ACAP 上加速任意精度整数乘法

• DOI: 10.1109/iccad57390.2023.10323754
• 发表时间: 2023-10
• 期刊: IEEE
• 作者: Yang, Zhuoping;Zhuang, Jinming;Yin, Jiaqi;Yu, Cunxi;Jones, Alex K.;Zhou, Peipei
• 通讯作者: Zhou, Peipei

SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration

SSR：用于变压器加速中延迟吞吐量权衡的空间顺序混合架构

• DOI: 10.1145/3626202.3637569
• 发表时间: 2024-04
• 期刊: ACM/SIGDA International Symposium on Field Programmable Gate Arrays
• 作者: Zhuang, Jinming;Yang, Zhuoping;Ji, Shixin;Huang, Heng;Jones, Alex K.;Hu, Jingtong;Shi, Yiyu;Zhou, Peipei
• 通讯作者: Zhou, Peipei

Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets

通过异构 Chiplet 实现大规模计算的挑战和机遇

• DOI: 10.1109/asp-dac58780.2024.10473961
• 发表时间: 2024-03
• 期刊: Asia and South Pacific Design Automation Conference (ASP-DAC
• 作者: Yang, Zhuoping;Ji, Shixin;Chen, Xingzhen;Zhuang, Jinming;Zhang, Weifeng;Jani, Dharmesh;Zhou, Peipei
• 通讯作者: Zhou, Peipei