Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications

合作研究：CMOS X：用于新兴计算应用的 CMOS 上大规模集成 FeFET 的设备到架构联合开发和演示

• 批准号: 2318807
• 负责人: Jie Gu
• 金额: $ 38.5万
• 依托单位: Northwestern University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-09-01 至 2026-08-31
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2318807&HistoricalAwards=false
• 关键词: Collaborative; Research; CMOS+X; Device; Architecture

In the new era of AI, modern computing electronics are facing tremendous challenges when a large amount of computing tasks, e.g. robotics, Augmented Reality and Virtual Reality (AR/VR), autonomous driving, require supports of gigantic computing models and enormous computing workloads. Such demands have dwarfed the capabilities of existing electronic hardware. As Complementary Metal Oxide Semiconductor (CMOS) technology approaches 1 nm node, it is obvious that the conventional technology scaling will soon run out of steam to meet the ever-growing demand of computing power. To continue the Moore’s law, Hafnium Oxide (HfO2) based ferroelectric field effect transistor (FeFET) is one of the leading candidates with benefits of combined nonvolatility, high energy efficiency, and compatibility with CMOS. While many device-level developments have been performed on FeFET, one of the hindering factors is that the device’s development is often performed at small scale without high-level integration with CMOS technology, which is necessary to deliver a complete integrated-circuit (IC) solution for supporting the modern computing tasks. To overcome the limitation of existing developments, this proposal will develop cross-layer techniques from device to circuit and architecture enabling large-scale integration of the highly promising FeFET device with standard CMOS technology. This project will perform full-stack developments from device to architecture for the integration of CMOS and FeFET technology targeting emerging computing applications. Fabricated FeFET with CMOS at advanced technology nodes at a large scale will be used to demonstrate the proposed techniques. More specifically, we will perform the following developments. At device level, improved process for integration between nFeFET, pFeFET and CMOS will be developed allowing better technology fusion of the FeFET and CMOS devices; At design methodology, a joint device-circuit collaborative design flow will be developed to tailor the FeFET technology towards the need of emerging computing applications such as AI; Furthermore, novel circuit and architecture utilizing FeFET as both memory and computing devices will be developed to exploit the features of FeFET and its co-existence with CMOS technology; Finally, demonstrations on complex processors and accelerators for emerging applications, with joint CMOS and FeFET technology will be delivered to showcase the benefits of the emerging device integrated with CMOS. The integrative approach and demonstration of CMOS and FeFET fusion will manifest the system perspective of FeFET devices and establish a solid foundation for the future FeFET developments especially for the emerging computing tasks. By integrating the advanced semiconductor technology with emerging computing tasks, the proposed projects provide strong educational materials and opportunities for students to learn the multi-disciplinary developments of modern computing techniques and microelectronic devices. Both course materials and workshops on frontier semiconductor and computing techniques will be developed to provide solid training to the society while also promoting diversity and inclusion to college STEM education.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

在人工智能新时代，现代计算电子面临着巨大的挑战，机器人、增强现实和虚拟现实（AR/VR）、自动驾驶等大量计算任务需要庞大的计算模型和巨大的计算工作量的支持。这些需求使现有电子硬件的能力相形见绌，随着互补金属氧化物半导体 (CMOS) 技术接近 1 nm 节点，传统技术的扩展显然很快就会失去动力。为了延续摩尔定律，基于氧化铪 (HfO2) 的铁电场效应晶体管 (FeFET) 是领先的候选者之一，具有非易失性、高能效和与 CMOS 的兼容性等优点。许多器件级开发都是在 FeFET 上进行的，阻碍因素之一是器件的开发通常是小规模的，没有与 CMOS 技术进行高级集成，而 CMOS 技术是提供完整的器件所必需的。为了克服现有开发的限制，该提案将开发从器件到电路和架构的跨层技术，从而实现极具前景的 FeFET 器件与标准 CMOS 的大规模集成。该项目将针对新兴计算应用进行从器件到架构的全堆栈开发，以先进技术节点大规模制造 FeFET，以更具体地演示所提出的技术。 ，我们将执行接下来，在器件层面，将开发 nFeFET、pFeFET 和 CMOS 之间的集成改进工艺，从而实现 FeFET 和 CMOS 器件更好的技术融合；在设计方法方面，将开发联合器件-电路协作设计流程，以定制 FeFET 技术。满足人工智能等新兴计算应用的需求；此外，将开发利用 FeFET 作为存储器和计算设备的新型电路和架构，以利用 FeFET 的特性及其与 CMOS 技术的共存；将提供针对新兴应用的复杂处理器和加速器的演示，以及 CMOS 和 FeFET 联合技术，以展示与 CMOS 集成的新兴器件的优势。 CMOS 和 FeFET 融合的集成方法和演示将体现 FeFET 器件和技术的系统前景。为未来 FeFET 的发展，特别是新兴计算任务奠定坚实的基础，通过将先进的半导体技术与新兴计算任务相结合，拟议项目为学生提供了强大的教育材料和学习现代计算的多学科发展的机会。将开发有关前沿半导体和计算技术的课程材料和研讨会，为社会提供扎实的培训，同时促进大学 STEM 教育的多样性和包容性。该奖项反映了 NSF 的法定使命，并被认为值得支持。通过使用基金会的智力优点和更广泛的影响审查标准进行评估。