ERI: FD-WiNoC: Area and Energy Efficient Full Duplex Transceiver System for Wireless Network on Chip

ERI：FD-WiNoC：用于片上无线网络的区域和节能全双工收发器系统

• 批准号: 2302010
• 负责人: Soumyasanta Laha
• 金额: $ 19.85万
• 依托单位: California State University-Fresno Foundation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-09-15 至 2025-08-31
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2302010&HistoricalAwards=false
• 关键词: ERI; FD; WiNoC; Area; Energy

The co-time co-frequency full-duplex wireless communication alleviates the issue of inefficient use of bandwidth in the existing co-time half-duplex communication. In the full-duplex mode, the transmission and reception of signals take place simultaneously in the same frequency band. The primary challenge in designing such a full-duplex wireless device is self-interference. The transmit signal which is locally generated in the transceiver and thus has a very high power level interferes with the low power received signal in the same frequency band. The received signal is thus submerged in the ‘self-interfered noise’ from the local transmitter and cannot be recovered. Several techniques have been suggested over the last decade to reduce the self-interference signal to the level where it can be neglected, thus eliminating self-interference. The current project targets to bring the self-interference cancellation to 60 dB or more, which is sufficient for on-chip wireless communications such as wireless network on chips (WiNoCs). The self-interference cancellation is particularly important for WiNOCs because WiNoCs will need high data rates (10 Gbps and beyond) to support today’s high performance multi-core computer architecture which require simultaneously bidirectional data transfer to support real-time applications. A full-duplex architecture will eliminate the need of two separate sets of frequency bands for transmission and reception, and hence reduce the demand of multiple sub-THz frequency bands by half. This help mitigate serious design challenges with CMOS technologies. The success of this research will motivate system-level study with advanced sub-20-nm RF FinFET technologies at 60 GHz and sub-THz frequencies to evaluate the performance of the proposed novel WiNoC architecture and compare it with other existing architectures. Furthermore, the validation of the full-duplex transceiver system for WiNoC applications will expand research insights for full-duplex capability of other on-chip communications such as wireless interconnects between chiplets or a wireless neural accelerator architecture. The project provides training opportunities for students, including those from underrepresented minority groups in STEM, to learn semiconductor integrated circuit design techniques and prepare themselves for future career in semiconductor industry. The project aims to develop a novel co-time co-frequency full-duplex transceiver system for wireless network on chip (WiNoC) applications in a cost-effective RF CMOS technology. The work is built on a preliminary feasibility study and will conduct fundamental research to improve the performance of the full-duplex transceiver circuit for WiNoC applications by the following research tasks: a) designing a novel energy- and area-efficient transmitter circuit with built-in analog cancellation, operating at 5 GHz and using the On-Off Keying (OOK) or other non-coherence modulation in a cost-effective 110-nm RF CMOS technology, to improve the self-interference cancellation to 40 dB or higher, b) designing a receiver front-end circuit at the same frequency and using the same technology with a novel high performance inductor-less low noise amplifier (LNA) for area efficiency, c) augmenting the above designs with self-interference cancellation in analog domain with the analog cancellation circuit and developing spectral estimation or other similar techniques to achieve a high digital cancellation of the residual signal to enhance the total self-interference cancellation to 60 dB or higher for practical applications of WiNoC, d) designing a prototype of the co-time co-frequency full-duplex transceiver system to validate all the performance parameters with experimental measurements as a proof of concept.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Co Time联合频率全简式无线通信减轻了现有的Co Time半双链通信中对带宽无效使用的问题。在全双工模式下，信号的传输和接收仅在同一频段中进行。设计这样的全双工无线设备的主要挑战是自我干扰。在收发器中局部生成的发射信号，因此具有很高的功率水平会干扰相同频带中接收到的低功率信号。因此，接收的信号被从本地发射器中淹没在“自我纠缠的噪声”中，无法恢复。在过去的十年中，已经提出了几种技术，以将自身解干信号降低到可以忽略的水平，从而消除自我干扰。当前的项目目标是使自我干扰取消取消至60 dB或更多，这足以足够芯片无线通信，例如芯片上的无线网络（Winocs）。自我干预取消对Winoc尤为重要，因为Winocs需要高数据速率（10 Gbps及以后）来支持当今的高性能多核计算机体系结构，这需要仅双向数据传输才能支持实时应用程序。完整的架构将消除两组用于传输和接收的频带的需求，因此将多个子THZ频段的需求减少了一半。这有助于通过CMOS技术缓解严重的设计挑战。这项研究的成功将通过60 GHz和Sub-Thz频率的高级20 nm RF FinFET技术激励系统级研究，以评估拟议中的新型Winoc体系结构的性能，并将其与其他现有体系结构进行比较。此外，对Winoc应用程序的全双工收发系统的验证将扩展研究见解，以了解其他芯片交流的全双工功能，例如芯片或无线神经加速器架构之间的无线互连。该项目为学生提供了培训机会，包括STEM中代表性不足的少数群体的培训机会，以学习半导体综合电路设计技术，并为在半导体行业的未来职业做准备。该项目旨在开发一种新颖的Co Time共同频率全双工收发器系统，用于在具有成本效益的RF CMOS技术中的芯片上无线网络（Winoc）应用程序。这项工作建立在初步的可行性研究基础上，并将进行基本研究，以通过以下研究任务来提高Winoc应用程序的全双工收发器电路的性能： b）以相同的频率设计接收器前端电路，并使用相同的技术使用新型的高性能引起的低噪声放大器（LNA）来设计接收器前端电路，以提高面积效率，c）增强上述设计，以自我干扰在模拟范围内进行模拟估算或相似的近距离估算，以实现模拟量估计或相似的光谱估算，以实现较高的型号，以实现模拟量的估计，或为了将Winoc的实际应用提高至60 dB或更高的总自我解释，d）设计合作时间的共同频率全双制收发器系统的原型，以验证所有绩效参数，并以实验性测量为概念证明，作为概念的证明。这一奖项反映了NSF的法定任务和稳定的构建，我们的稳定构成了我们的构成，我们的构建是诚实的。 标准。