Collaborative Research: SHF: Medium: Automated energy-efficient sensor data winnowing using native analog processing

协作研究：SHF：中：使用本机模拟处理进行自动节能传感器数据筛选

• 批准号: 2212346
• 负责人: Jiang Hu
• 金额: $ 30万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2022
• 资助国家: 美国
• 起止时间: 2022-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2212346&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; Medium; Automated

As computing becomes pervasive in all aspects of daily life, computing hardware must allow for increasing interaction with the physical world. This interaction takes the form of sensed signals that are analog in nature, e.g., a sensor may output a voltage that can take on a continuous range of values. Traditional mainstream computing digitizes this data, converting it to digital 0s and 1s for efficient analysis and processing. However, as the amount of sensed analog data is growing exponentially, digital processors will be faced with a data deluge from external sensors. For these vast volumes of data, even the cost of converting analog input data to digital signals, prior to any processing, can be prohibitively expensive. Native analog processing (NAP) negates the need for analog-to-digital conversion by working in the analog domain. NAP can be used to implement data processing functions inexpensively, but can achieve only limited accuracy; on the other hand, digital processing can achieve high accuracy, but requires the overhead of analog-to-digital conversion. This project presents a methodology for mixed-signal processing that hybridizes digital and analog subcircuit implementations to achieve the best of both worlds. The effort intends to actively engage with the semiconductor industry, and will train graduate and undergraduate students in the area of semiconductor design, thus alleviating the national skills shortage in this area.In the first step, computing tasks are automatically partitioned into hybrid analog/digital segments, with the goal of meeting system-level constraints on throughput, power, and noise/error. The computations associated with a task are abstractly represented by a dataflow graph (DFG). This representation is widely used to model a variety of tasks, including those commonly used in digital signal processing and machine learning. The nodes in the DFG are mapped to analog or digital implementations, using cost functions that represent the cost of implementation, as well as the cost of any required analog-to-digital or digital-to-analog conversion. Next, the analog and digital circuitry is optimized to build a silicon implementation at the layout level, based on cutting-edge transistor technologies, which involve restrictive design rules that impose limitations such as unidirectional routing and gridded layout. The optimizations are facilitated by novel techniques for back-end analysis, synthesis, and implementation developed in this project, including transistor and interconnect optimizations, placement and routing techniques that are specifically targeted to mixed-signal designs, and compact performance machine-learning-based model generation that efficiently predicts circuit performance. The project thus automatically translates the system-level DFG specification of a computing task to an optimized mixed-signal silicon implementation.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

随着计算在日常生活的各个方面变得普遍，计算硬件必须允许增加与物理世界的交互。这种相互作用采用本质上是模拟的感测信号的形式，例如，传感器可以输出可以呈现连续范围值的电压。传统主流计算将这些数据数字化，将其转换为数字 0 和 1，以便进行高效的分析和处理。然而，随着感测到的模拟数据量呈指数级增长，数字处理器将面临来自外部传感器的海量数据。 对于如此大量的数据，即使在进行任何处理之前将模拟输入数据转换为数字信号的成本也可能非常昂贵。 本机模拟处理 (NAP) 通过在模拟域中工作，无需进行模数转换。 NAP可以廉价地实现数据处理功能，但只能达到有限的精度；另一方面，数字处理可以实现高精度，但需要模数转换的开销。该项目提出了一种混合信号处理方法，该方法混合了数字和模拟子电路实现，以实现两全其美。该项目旨在积极参与半导体行业，培养半导体设计领域的研究生和本科生，从而缓解该领域的国家技能短缺问题。第一步，计算任务自动划分为混合模拟/数字段，目标是满足吞吐量、功耗和噪声/错误的系统级限制。与任务相关的计算由数据流图（DFG）抽象表示。这种表示形式广泛用于对各种任务进行建模，包括数字信号处理和机器学习中常用的任务。 DFG 中的节点使用表示实施成本以及任何所需的模数或数模转换成本的成本函数映射到模拟或数字实施。接下来，基于尖端晶体管技术，对模拟和数字电路进行优化，以在布局级别构建硅实现，其中涉及限制性设计规则，这些规则施加了单向布线和网格布局等限制。该项目中开发的后端分析、综合和实现的新技术促进了优化，包括晶体管和互连优化、专门针对混合信号设计的布局和布线技术，以及基于机器学习的紧凑性能有效预测电路性能的模型生成。因此，该项目自动将计算任务的系统级 DFG 规范转换为优化的混合信号芯片实现。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力优点和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Performance-driven Wire Sizing for Analog Integrated Circuits

模拟集成电路性能驱动的布线尺寸

• DOI: 10.1145/3559542
• 发表时间: 2022-08-26
• 期刊: ACM Transactions on Design Automation of Electronic Systems
• 影响因子: 1.4
• 作者: Yaguang Li;Yishuang Lin;Meghna Madhusudan;A. Sharma;S. Sapatnekar;R. Harjani;Jiang Hu
• 通讯作者: Jiang Hu