CNS Core:Small:A HW/SW Codesign Framework For Dynamic Composition of Disaggregated Hardware Systems Securely
CNS 核心:小型:用于安全地动态组合分解硬件系统的硬件/软件协同设计框架
基本信息
- 批准号:2225882
- 负责人:
- 金额:$ 59.99万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2022
- 资助国家:美国
- 起止时间:2022-10-01 至 2025-09-30
- 项目状态:未结题
- 来源:
- 关键词:
项目摘要
Traditionally datacenters and high performance computing (HPC) facilities increase compute capacity by adding additional servers, which is increasingly becoming inefficient since emerging workloads exhibit very high peak to average memory requirements. Moreover, the fundamental building blocks of a modern data centers and HPC facilities (the processors) are becoming increasingly specialized with dedicated hardware for vector/tensor processing, deep learning, different memory pools such as DRAM, SRAM, and NVRAM, and special-purpose interconnect. Replicating such processors invariably results in hardware that is neither required nor useful all the time by all the applications. A disaggregated approach to computing system design can overcome these inefficiencies by selecting and composing the required hardware resources (e.g., accelerators, memory) to meet the requirements of a specific workflow or application. This project aims to make the design and implementation of such systems practical by addressing system security and performance. The intellectual merit of the proposed work lies in developing a new hardware software/codesign framework that is based on virtualized remote memory, object-level tracking for efficient data tiering and coherence, and flexible mechanisms to create and enforce hardware-based trusted execution environments. We will evaluate our solutions using a rigorous evaluation plan based on system-level modeling and simulation using the gem5 software infrastructure.Artificial intelligence and machine learning are expected to accelerate scientific discovery and play a very crucial role in addressing the grand challenges of the 21st century such as climate change, sustainability, and drug/vaccine discovery with broad societal impact. This project will enable training large scale machine learning models and perform large scale data analytics on disaggregated hardware systems which will allow them to be more performant and cost-effective. In addition, the modeling and simulation environment in gem5 broadly impacts computer architecture and computer systems researchers beyond this project. The models created in this project will be committed to the upstream gem5 project so that other researchers can use these models and build off of our designs. These contributions will impact the reproducibility and sustainability of this software infrastructure and advance computer architecture research in general.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
传统上,数据中心和高性能计算 (HPC) 设施通过添加额外的服务器来提高计算能力,但由于新兴工作负载表现出非常高的峰值平均内存需求,这种做法变得越来越低效。此外,现代数据中心和 HPC 设施(处理器)的基本构建模块正变得越来越专业化,包括用于矢量/张量处理、深度学习、不同内存池(例如 DRAM、SRAM 和 NVRAM)以及专用硬件的专用硬件。互连。 复制此类处理器总是会导致所有应用程序始终不需要或无用的硬件。计算系统设计的分解方法可以通过选择和组合所需的硬件资源(例如加速器、内存)来满足特定工作流程或应用程序的要求,从而克服这些低效率问题。该项目旨在通过解决系统安全性和性能问题,使此类系统的设计和实现变得实用。所提议工作的智力优点在于开发一种新的硬件软件/协同设计框架,该框架基于虚拟化远程内存、用于高效数据分层和一致性的对象级跟踪,以及创建和实施基于硬件的可信执行环境的灵活机制。我们将使用基于gem5软件基础设施的系统级建模和仿真的严格评估计划来评估我们的解决方案。人工智能和机器学习有望加速科学发现,并在应对21世纪的巨大挑战中发挥非常关键的作用例如气候变化、可持续性以及具有广泛社会影响的药物/疫苗发现。 该项目将能够训练大规模机器学习模型,并在分类硬件系统上执行大规模数据分析,从而提高性能和成本效益。此外,gem5 中的建模和仿真环境广泛影响了本项目之外的计算机体系结构和计算机系统研究人员。该项目中创建的模型将致力于上游 gem5 项目,以便其他研究人员可以使用这些模型并基于我们的设计进行构建。这些贡献将影响该软件基础设施的可重复性和可持续性,并总体上推进计算机体系结构研究。该奖项反映了 NSF 的法定使命,并通过使用基金会的智力价值和更广泛的影响审查标准进行评估,被认为值得支持。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Venkatesh Akella其他文献
Venkatesh Akella的其他文献
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{{ truncateString('Venkatesh Akella', 18)}}的其他基金
IUCRC Planning Grant UC Davis: Center for Memory System Research (CMEMSYS)
IUCRC 规划拨款 加州大学戴维斯分校:记忆系统研究中心 (CMEMSYS)
- 批准号:
2310924 - 财政年份:2023
- 资助金额:
$ 59.99万 - 项目类别:
Standard Grant
CCF: Small: Improving Trace Based Simulation of On-Chip Networks
CCF:小型:改进片上网络基于跟踪的仿真
- 批准号:
1116897 - 财政年份:2011
- 资助金额:
$ 59.99万 - 项目类别:
Standard Grant
Programmable Architectures for Low Density Parity Check Codes
低密度奇偶校验码的可编程架构
- 批准号:
0429154 - 财政年份:2004
- 资助金额:
$ 59.99万 - 项目类别:
Continuing Grant
CAREER: Making Asynchronous Design Practical
职业:使异步设计变得实用
- 批准号:
9702302 - 财政年份:1997
- 资助金额:
$ 59.99万 - 项目类别:
Continuing Grant
RIA: High-Level Synthesis of Self-Timed Circuits
RIA:自定时电路的高级综合
- 批准号:
9308668 - 财政年份:1993
- 资助金额:
$ 59.99万 - 项目类别:
Standard Grant
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