Collaborative Research: SHF: Medium: A Comprehensive Modeling Framework for Cross-Layer Benchmarking of In-Memory Computing Fabrics: From Devices to Applications

协作研究：SHF：Medium：内存计算结构跨层基准测试的综合建模框架：从设备到应用程序

• 批准号: 2212239
• 负责人: Michael Niemier
• 金额: $ 92.15万
• 依托单位: University of Notre Dame
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2022
• 资助国家: 美国
• 起止时间: 2022-09-01 至 2026-08-31
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2212239&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; Medium; Comprehensive

This project will develop a framework for rapid and accurate design-space explorations of application-level workloads assuming technology-enabled in-memory computing (IMC), which is at present being investigated for a range of application spaces (AI/machine learning, bioinformatics, graph processing, etc.). IMC is of great interest as more and more compute workloads must process ever growing amounts of data. Frequently, the energy and latency associated with data transfer from a computer’s memory to a processor can overwhelm the cost of the processing itself. As such, it is highly desirable to co-locate processing and memory. Work in the project will result a publicly available, curated framework that leverages both existing device models and design tools, and that incorporates new device models and design tools to properly evaluate the IMC design space with at-scale, application-level workloads. A modeling and evaluation infrastructure will be developed to address the above design/evaluation challenges as there is an obvious need to explore a vast design space. Investigators in this project will also work with K-8 teachers to augment existing STEM curricula with material that exposes students to fundamental concepts and skills in computer science. This is especially relevant as computer science concepts are now assessed on state-wide standardized tests. Students from under-represented groups will be recruited and mentored via REU experiences.To explore the IMC design space, device-level modeling, circuit/architectural-level modeling, device non-ideality (e.g., variation) analysis, and ways to integrate heterogeneous architectural solutions that target specific application-level workloads must all be studied. In the IMC space, (i) the number of candidate technologies is large and ever-changing, (ii) multiple candidate IMC circuits and architectures – e.g., computing at the array periphery (CAP), content addressable memories (CAMs) and crossbars – exist, (iii) IMC solutions may be more susceptible to device variations/non-idealities, and this impact must be captured at the application level, (iv) emerging technology-enabled IMC solutions may be used with existing architectural solutions and/or in a variety of heterogenous designs, and (v) there are effectively an infinite number of application-level mappings/potential algorithmic changes that one might consider. With respect to device models, there is a deliberate focus on ferroelectric devices – i.e., front-end-of-line silicon ferroelectric field effect transistors, back-end-of-line metal-oxide ferroelectric field effect transistors, and multi-gate ferroelectric field effect transistors – owing to ever-growing interest in this technology as well as the need to consider monolithic 3D processing/memory systems. For IMC circuits/architectures, this project will expand and develop modeling/evaluation tools for two different “flavors” of computing in memory – (i) CAMs (that can report memory entries that best match a given query) and (ii) CAP. For CAMs, representative efforts include projecting figures of merit for binary, ternary, multi-level, and analog CAM arrays (read/write energy and latency, etc.) designs implemented with different non-volatile memories, for different matching functions. Determining optimal CAM array sizes and other design parameters will also be considered. Evaluation of CAP designs for different NVMs will also be developed. For applications, solutions based on IMC fabrics for a subset of applications from MLPerf will be evaluated. MLPerf represents a consortium of AI leaders who have derived relevant workloads for vision, language, etc.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

该项目将开发用于应用程序级工作负载技术技术中的快速，准确的设计空间探索，目前正在研究一系列应用空间（AI/机器学习，生物信息学，图形处理，，图形处理，等等。设计工具，并结合了新的设备模型和设计工具，以适当地评估IMC设计空间，因为显然需要探索庞大的设计空间，因此在上面的设计/评估挑战上为上述设计/评估挑战该项目还会与材料一起使用K-8教师进行辅助课程。空间，设备级建模，电路/级别G，设备非理想性（例如变化）分析以及整合目标特定应用程序的异质体系解决方案的方法 - 必须在IMC空间中研究。候选技术是庞大且不断变化的rcuits和架构 - 例如，在阵列外围（CAP）的计算，内容可寻址的记忆（CAMS）和横栏 - 存在，IMC解决方案可能会更多，并且必须在应用程序中捕获该法案。级别，（iv）新兴技术的IMC解决方案可以与现有的体系解决方案和/或各种异质设计一起使用，并且（v）有效地存在VEL映射/潜在算法变化的变化，这些变化的变化将变化对设备模型的变化变化。 ，故意关注铁电设备-I.E。，前端的唱片独剪影磁场效应晶体管效应晶体管以及多栅极铁电场效应晶体效应晶体管晶体管晶体管晶体管对这项技术的不断增长，因此需要考虑整体岩石。 3D处理/内存系统。对于CAMS，代表性的启示包括功绩二进制的图形，三元级级别和模拟凸轮阵列（读/写能量和延迟等），以不同的非挥发性记忆实现。对于应用程序，将评估基于IMC织物的解决方案，以评估MLPERF的一部分应用程序。

项目成果

Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures

• DOI: 10.23919/date56975.2023.10136923
• 发表时间: 2023-04
• 期刊: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)
• 作者: M. Niemier;X.S. Hu;L. Liu;M. Sharifi;I. O’Connor;David Atienza Alonso;G. Ansaloni;Can Li;Asif Khan;Daniel C. Ralph