SHF: Small: Automatic Generation of Cache Coherent Memory Systems for Multicore Processors

SHF：小型：自动生成多核处理器的缓存一致性内存系统

基本信息

批准号：
2002737
负责人：
Daniel Sorin
金额：
$ 40万
依托单位：
Duke University
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2020
资助国家：
美国
起止时间：
2020-07-01 至 2024-06-30
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=2002737&HistoricalAwards=false
关键词：
SHF Small Automatic Generation Cache

项目摘要

Today’s computer processors are called multicore processors, because they have multiple processor cores in them, all of which can be working simultaneously on computational tasks. These cores share data with each other using a communication protocol called cache coherence, which ensures that the data used by these cores is up-to-date and correct. Cache coherence protocols are notoriously complicated and difficult to design, and they are at least as difficult to then verify as being correct in all situations. Because of their complexity, coherence protocols take a large and disproportionate share of the design and verification resources when the computer industry creates a new processor. Furthermore, the difficulty of designing coherence protocols is increasing as processor cores scale up in variety and number on a single chip. This project is developing a novel tool that enables computer architects to quickly and easily design high-performance coherence protocols that are provably correct. The tool has the potential to radically change the way that protocols are designed, in both industry and academia, and thus make processor design faster, cheaper, and more reliable. Through an outreach program and a research fellowship program for undergraduates, the project will benefit from the contributions of women, under-represented populations, and undergraduate researchers.As processor designs change--with the addition of more cores or different types of cores, or with different expected communication patterns--there are incentives to create new coherence protocols to suit these changes. Even if a new protocol is not a radical departure from previous protocols, designing it and validating it are arduous, bug-prone processes.This project is developing a novel tool, called ProtoGen+, for automating the design of verifiable cache coherence protocols. The architects need only provide simplified protocol designs that omit complexity like hierarchy and concurrent communications. The tool takes those simplified protocol designs and automatically generates the high-performance versions of those protocols, thus hiding the complexity from the architects. ProtoGen+ then outputs the complicated, concurrent protocol. ProtoGen+ greatly reduces design and verification effort and minimizes the number of design bugs. ProtoGen+ accommodates a wide range of protocols, including those with hierarchy and heterogeneity. ProtoGen+ also generates the virtual network assignments necessary to avoid protocol deadlock. Two secondary objectives of the work are to explore the space of protocols that are compatible with ProtoGen+ and to produce protocols that are compatible with the previously developed Neo framework for verifiable protocol design.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

今天的计算机处理器被称为多核处理器，因为它们内部有多个处理器核心，所有这些核心都可以同时处理计算任务，这些核心使用称为缓存一致性的通信协议相互共享数据，从而确保所使用的数据。这些核心是最新且正确的，众所周知，缓存一致性协议非常复杂且难以设计，并且由于其复杂性，它们至少在所有情况下都难以验证。当计算机行业创建新的处理器时，设计和验证资源的份额不成比例。此外，随着单芯片上处理器内核的种类和数量的增加，设计一致性协议的难度也在增加。计算机架构师可以快速轻松地设计可证明正确的高性能一致性协议，该工具有可能从根本上改变工业界和学术界的协议设计方式，从而使处理器设计更快、更便宜、更可靠。 .通过外展计划和这是一个针对本科生的研究奖学金计划，该项目将受益于女性、代表性不足的人群和本科生研究人员的贡献。随着处理器设计的变化——添加更多内核或不同类型的内核，或者不同的预期通信模式——有动机创建新的一致性协议来适应这些变化，即使新协议与以前的协议没有根本不同，但设计和验证它是艰巨的、容易出现错误的过程。这个项目正在开发一种新颖的工具，称为 ProtoGen+，用于自动化可验证缓存一致性协议的设计，架构师只需要提供简化的协议设计，从而省略层次结构和并发通信等复杂性。该工具采用这些简化的协议设计并自动生成这些协议的高性能版本，从而隐藏了复杂性。 ProtoGen+ 然后输出复杂的并发协议，ProtoGen+ 大大减少了设计和验证工作，并最大限度地减少了设计错误的数量，包括具有层次结构和异构性的协议。 ProtoGen+ 还生成避免协议死锁所需的虚拟网络分配，该工作的两个次要目标是探索与 ProtoGen+ 兼容的协议空间以及与先前开发的 Neo 框架兼容的可验证协议设计。授予 NSF 的法定使命，并通过评估反映使用基金会的智力优点和更广泛的影响审查标准，被认为值得支持。

项目成果

期刊论文数量（2）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols

HeteroGen：异构缓存一致性协议的自动综合

DOI：
发表时间：
2022-04
期刊：
28th IEEE International Symposium on High-Performance Computer Architecture
影响因子：
0
作者：
Oswald, Nicolai;Nagarajan, Vijay;Sorin, Daniel;Gavrielatos, Vasilis;Olausson, Theo;Carr, Reece
通讯作者：
Carr, Reece

HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols

HeteroGen：异构缓存一致性协议的自动综合

DOI：
发表时间：
2022-04
期刊：
28th IEEE International Symposium on High-Performance Computer Architecture
影响因子：
0
作者：
Oswald, Nicolai;Nagarajan, Vijay;Sorin, Daniel;Gavrielatos, Vasilis;Olausson, Theo;Carr, Reece
通讯作者：
Carr, Reece