IRES Track I:Collaborative Research:Application-Specific Asynchronous Deep Learning IC Design for Ultra-Low Power

IRES 轨道 I：协作研究：超低功耗专用异步深度学习 IC 设计

• 批准号: 1951488
• 负责人: Na Gong
• 金额: $ 10万
• 依托单位: University of South Alabama
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2020
• 资助国家: 美国
• 起止时间: 2020-09-01 至 2024-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1951488&HistoricalAwards=false
• 关键词: IRES; Track; Collaborative; Research; Application

This 3-year IRES Track I project recruits three cohorts of U.S. students to conduct research in China, with the major research goal as developing, fabricating, and testing an ultra-low power application-specific deep learning integrated circuit, and evaluating its performance through the integration with physical Internet-of-Things (IoT) edge computing devices. It brings together three research groups with unique expertise from University of Arkansas (ultra-low power asynchronous circuit design), University of South Alabama (context-aware memory design), and Peking University, China (deep learning algorithm development and optimization). The expected research outcomes will accelerate edge computing for a large variety of IoT applications such as advanced medical and elderly care systems, and self-driving vehicles. Each year six U.S. student participants work onsite at Peking University for eight weeks, leveraging the onsite research facilities. The multicultural, multidisciplinary nature of this project provides a unique training and career preparation opportunity for the participating students, including multidisciplinary discussion, teamwork, effective communication, and technical writing. The PIs continue their prior efforts in recruiting student participants from underrepresented and minority groups, leveraging their contacts and the existing mechanisms at each university. The research outcomes and the student experience will be disseminated nation-wide for benefiting the research community and encouraging more students to participate in similar programs.Deep learning is transforming many modern Artificial Intelligence (AI) applications, in many of which deep learning has begun to exceed human performance. However, the superior performance of deep learning comes at the cost of extremely high computational complexity associated with large datasets. Therefore, deep learning algorithms are traditionally implemented in software and executed on powerful general-purpose cloud computing platforms. In contrast to the prevailing research in general-purpose counterparts, the application-specific deep learning IC has much lower power consumption, thereby ideal for integration with power-constrained IoT devices. This IRES project is to develop, fabricate, and test an ultra-low power deep learning integrated circuit (IC), and evaluate its performance through the integration with physical IoT edge computing devices. Technical innovations to be developed by the student participants include: 1) optimization of application-specific deep learning algorithms for alleviating the requirements of hardware implementation; 2) delay-insensitive asynchronous circuit design for substantially improved energy efficiency; and 3) context-aware memory development for power savings and low implementation cost. This project uniquely connects deep learning algorithm optimization, asynchronous circuit design, and memory optimization together to achieve a highly optimized system, which will benefit the semiconductor and AI societies at large by the revolutions in hardware-tailored deep learning algorithms and specialized computing hardware. It is expected that this research will demonstrate the advantages of application-specific deep learning hardware and layout the foundation of a new and promising direction for both academic research and industrial development.This project is jointly funded by the Office of International Science and Engineering (OISE) and the Established Program to Stimulate Competitive Research (EPSCoR).This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

这项为期3年的IRES Track I Project招募了三名美国学生在中国进行研究，主要的研究目标是开发，制造和测试超低功率应用特定的深度学习集成电路，并通过与物理互联网（IoT）边缘计算设备进行集成来评估其性能。它汇集了三个研究小组，这些研究小组具有来自阿肯色大学的独特专业知识（超低功率异步电路设计），南阿拉巴马大学（上下文感知记忆设计）和中国北京大学（深度学习算法的开发和优化）。预期的研究结果将加速各种物联网应用，例如高级医疗和老年护理系统以及自动驾驶汽车的优势计算。每年有六名美国学生参与者在北京大学现场工作八周，利用现场研究设施。该项目的多元文化，多学科的性质为参与学生提供了独特的培训和职业准备机会，包括多学科讨论，团队合作，有效的沟通和技术写作。 PI继续他们先前的努力，从而从代表性不足和少数群体中招募学生参与者，利用他们的联系和每所大学的现有机制。研究成果和学生的经验将在全国范围内传播，以使研究社区受益并鼓励更多的学生参与类似的计划。深度学习正在改变许多现代人工智能（AI）应用程序，其中许多深度学习已经开始超越人类的表现。但是，深度学习的出色表现是以与大数据集相关的极高计算复杂性为代价。因此，深度学习算法传统上是在软件中实现的，并在功能强大的通用云计算平台上执行。与通用同行的普遍研究相反，应用特定的深度学习IC具有较低的功耗，因此非常适合与功能约束的物联网设备集成。 IRES项目是开发，制造和测试超低功率深度学习集成电路（IC），并通过与物理物联网边缘计算设备的集成来评估其性能。学生参与者将开发的技术创新包括：1）优化针对特定应用的深度学习算法，以减轻硬件实施的要求； 2）延迟不敏感的异步电路设计，可大大提高能源效率； 3）节省功率和低实施成本的上下文感知内存开发。该项目独特地连接了深度学习算法优化，异步电路设计和内存优化，以实现高度优化的系统，这将使半导体和AI社会受益于硬件深度深度学习算法和专业计算硬件的革命。可以预期，这项研究将证明特定应用的深度学习硬件的优势，并布局为学术研究和工业发展的新方向提供了基础。该项目由国际科学与工程办公室（OISE）（OISE）（OISE）（OISE）（OISE）共同资助，并既定的计划，以及启发竞争性研究（EPSSCOR）的范围内的Infort of Suter the Internition the dee eyt the Infortial the Inder the Inder te eyt the Inder te eym eyt eym a奖，这是由deem eyt eym te eyt eym eyt awort授予的。影响审查标准。