SHF: Small: Minimizing System Level Testing of Processor SOCs

SHF：小型：最大限度地减少处理器 SOC 的系统级测试

基本信息

批准号：
1910964
负责人：
Adit Singh
金额：
$ 49.99万
依托单位：
Auburn University
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2019
资助国家：
美国
起止时间：
2019-08-01 至 2024-07-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1910964&HistoricalAwards=false
关键词：
SHF Small Minimizing System Level

项目摘要

Integrated circuits (ICs), and more complex Systems-on-Chip (SOCs), are at the heart of all modern computing and communication systems, ranging from cell phones to cloud computing systems. In these complex electronic parts, billions of individual circuit components are incorporated on less than a square inch of silicon. Unfortunately, such microscopic components are subject to manufacturing defects and variations that can significantly impact the performance and dependability of the IC. This project aims at significantly improving the post manufacturing testing of ICs to reliably detect and screen out defective and marginal parts before they are assembled into larger end-use devices and systems. The goal is to reduce manufacturing costs and increase the reliability of electronic systems. More broadly, the project is expected to strengthen the educational and research programs at Auburn University, and enhance the pool of engineering talent available to the growing electronics, automotive and aerospace industries in Alabama, and the nation.Traditionally, electrical post manufacturing tests for ICs are developed to check for the different possible failure scenarios on a target list of likely manufacturing faults. The tests exercise the IC to rule out the existence of nearly all the targeted failures within just a few seconds. Unfortunately, it has been increasingly observed that such targeted tests fail to catch many malfunctioning parts that end up in assembled systems. Consequently, industry has been forced to introduce a new type of test that extensively exercises newly manufactured ICs in actual functional operation for sufficiently long, usually at least ten to fifteen minutes, to check for fully correct functioning. These new System Level Tests (SLTs) significantly increase test cost. This project is investigating an innovative adaptive approach for minimizing costs by avoiding SLT for a significant fraction of the manufactured ICs. This is achieved by accurately predicting the likelihood of each IC failing SLT based on available traditional test results, using innovative prediction methods, including machine learning. It is expected that for more than half the manufactured parts, this probability will be small enough for the IC to skip SLT without materially degrading overall system reliability, thereby resulting in significant test cost savings.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

集成电路 (IC) 和更复杂的片上系统 (SOC) 是所有现代计算和通信系统（从手机到云计算系统）的核心。在这些复杂的电子部件中，数十亿个单独的电路元件集成在不到一平方英寸的硅片上。不幸的是，这种微型元件容易出现制造缺陷和变化，从而严重影响 IC 的性能和可靠性。该项目旨在显着改进 IC 的制造后测试，以便在将其组装成更大的最终用途设备和系统之前可靠地检测和筛选出有缺陷和边缘的部件。目标是降低制造成本并提高电子系统的可靠性。更广泛地说，该项目预计将加强奥本大学的教育和研究项目，并为阿拉巴马州和全国不断发展的电子、汽车和航空航天工业增加工程人才库。传统上，IC 的电气后制造测试开发用于检查可能的制造故障目标列表中不同可能的故障场景。这些测试使 IC 在短短几秒钟内排除几乎所有目标故障的存在。不幸的是，人们越来越多地观察到，此类有针对性的测试无法发现组装系统中最终出现的许多故障部件。因此，业界被迫引入一种新型测试，在实际功能操作中广泛测试新制造的 IC 足够长的时间（通常至少十到十五分钟），以检查功能是否完全正确。这些新的系统级测试 (SLT) 显着增加了测试成本。该项目正在研究一种创新的自适应方法，通过避免大部分已制造 IC 的 SLT 来最大限度地降低成本。这是通过使用机器学习等创新预测方法，根据可用的传统测试结果，准确预测每个 IC 失败 SLT 的可能性来实现的。预计对于一半以上的制造零件来说，这种概率足够小，足以让 IC 跳过 SLT，而不会严重降低整体系统的可靠性，从而显着节省测试成本。该奖项反映了 NSF 的法定使命，并被认为是值得的通过使用基金会的智力优势和更广泛的影响审查标准进行评估来获得支持。

项目成果

期刊论文数量（8）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Silent Error Corruption: The New Reliability and Test Challenge

无声错误损坏：新的可靠性和测试挑战

DOI：
10.1109/lats58125.2023.10154487
发表时间：
2023-03
期刊：
2023 IEEE Latin America Test Symposium
影响因子：
0
作者：
Singh; Adit D.
通讯作者：
Adit D.

Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts

两种模式时序测试捕获缺陷引起的短路多栅极延迟影响

DOI：
10.1109/vts50974.2021.9441005
发表时间：
2021-04
期刊：
2021 IEEE 39th VLSI Test Symposium (VTS
影响因子：
0
作者：
Pandey, Sujay;Liao, Zhiwei;Nandi, Shreyas;Natarajan, Suriyaprakash;Sinha, Arani;Singh, Adit;Chatterjee, Abhijit
通讯作者：
Chatterjee, Abhijit

Exploring the Mysteries of System-Level Test

探索系统级测试的奥秘

DOI：
10.1109/ats49688.2020.9301557
发表时间：
2020-11
期刊：
2020 IEEE Asian Test Symposium
影响因子：
0
作者：
Polian, Ilia;Anders, Jens;Becker, Steffen;Bernardi, Paolo;Chakrabarty, Krishnendu;ElHamawy, Nourhan;Sauer, Matthias;Singh, Adit;Reorda, Matteo Sonza;Wagner, Stefan
通讯作者：
Wagner, Stefan

A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture

使用扫描架构的回收 IC 零成本检测方法