SHF: Small: Addressing Challenges for the Next Decade of Massively Parallel NUMA Accelerators

SHF：小型：应对大规模并行 NUMA 加速器未来十年的挑战

• 批准号: 1910924
• 负责人: Timothy Rogers
• 金额: $ 49.54万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-10-01 至 2023-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1910924&HistoricalAwards=false
• 关键词: SHF; Small; Addressing; Challenges; Next

The physical and economic principles that enabled Dennard scaling and Moore's law in the semiconductor industry have reached their breaking point. However, as the number of transistors economically fabricated on a single chip plateaus, the processor industry has pivoted to create single-package computing systems, composed of multiple sub-components known as chiplets. Chiplets, which communicate via high-bandwidth on-package networks, offer the potential for transparent performance scaling into the next decade. However, chiplets introduce challenging non-uniform memory access characteristics into single-package systems that have traditionally not been subject to these effects. This project develops techniques to overcome the challenges of non-uniform memory accesses on high-performance single- and multi-package systems without programmer intervention. Exploring programmer-transparent scaling mechanisms improves the portability and lifetime of programs, decreasing the cost and complexity of software. Through the creation of course content and undergraduate summer internships, the project fosters an understanding of how to program machines in a post-Moore world and how compute accelerators should be designed to minimize the impact on the end-programmer as system complexity increases.This project develops coordinated data placement and thread scheduling algorithms that leverage static information from the compiler and dynamic information from the runtime system to inform data placement and hardware-based thread scheduling. It advances the state-of-the-art by developing an open-source Graphic Processing Unit (GPU) simulator with a hierarchical interconnect that can be used to model both chiplet-based GPUs and multi-GPU systems. The researchers are exploring compiler informed data placement and thread scheduling in GPUs. Initial results demonstrate that a static analysis of the code can predict the data accessed by GPU threadblocks. Analysis shows that it is possible to determine which threads in a grid share memory pages, and the manner of that sharing, by building new static techniques that add an additional dimension to decades of work on compilers for sequential code. Using static information, in combination with runtime information provided by GPU drivers, the researchers are developing advanced data placement, prefetching, and thread scheduling algorithms. Both future chiplet-based designs and existing multi-GPU systems benefit from the development of these algorithms. Looking beyond the high-bandwidth memory used in GPUs today the project explores the system-level implications of heterogeneous memory in a chiplet-based system. Data placement and thread scheduling have even more importance in GPU systems of the future that make use of high bandwidth memory, traditional dynamic random-access memory, and non-volatile memory. The problem sizes in such systems are anticipated to be so large that opportunistic data placement and thread scheduling are even more critical than in conventional systems. The project uses sharing patterns based on the inter-kernel producer-consumer nature of machine learning workloads to change the program's code layout, runtime data placement, and threadblock scheduling algorithm to maximize locality in multi-node systems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

在半导体行业中实现登纳德缩放定律和摩尔定律的物理和经济原理已经达到了临界点。然而，随着在单芯片上经济地制造的晶体管数量趋于稳定，处理器行业已转向创建单封装计算系统，该系统由多个称为小芯片的子组件组成。小芯片通过高带宽封装网络进行通信，为未来十年的透明性能扩展提供了潜力。然而，小芯片将具有挑战性的非均匀存储器访问特性引入到传统上不受这些影响的单封装系统中。该项目开发的技术可克服高性能单封装和多封装系统上非均匀内存访问的挑战，而无需程序员干预。探索程序员透明的扩展机制可以提高程序的可移植性和生命周期，从而降低软件的成本和复杂性。通过创建课程内容和本科生暑期实习，该项目促进了人们对如何在后摩尔世界中对机器进行编程以及如何设计计算加速器以最大限度地减少系统复杂性增加时对最终程序员的影响的理解。该项目开发协调的数据放置和线程调度算法，利用来自编译器的静态信息和来自运行时系统的动态信息来通知数据放置和基于硬件的线程调度。它通过开发具有分层互连的开源图形处理单元 (GPU) 模拟器来推进最先进的技术，该模拟器可用于对基于小芯片的 GPU 和多 GPU 系统进行建模。研究人员正在探索 GPU 中编译器通知的数据放置和线程调度。初步结果表明，代码的静态分析可以预测 GPU 线程块访问的数据。分析表明，通过构建新的静态技术，可以确定网格中的哪些线程共享内存页面以及共享的方式，这些技术为序列代码编译器数十年的工作增加了额外的维度。研究人员正在使用静态信息与 GPU 驱动程序提供的运行时信息相结合来开发高级数据放置、预取和线程调度算法。未来基于小芯片的设计和现有的多 GPU 系统都受益于这些算法的开发。除了当今 GPU 中使用的高带宽内存之外，该项目还探讨了基于小芯片的系统中异构内存的系统级影响。数据放置和线程调度在未来使用高带宽内存、传统动态随机存取内存和非易失性内存的 GPU 系统中更加重要。预计此类系统中的问题规模非常大，以至于机会性数据放置和线程调度比传统系统更为重要。该项目使用基于机器学习工作负载的内核间生产者-消费者性质的共享模式来改变程序的代码布局、运行时数据放置和线程块调度算法，以最大限度地提高多节点系统中的局部性。该奖项反映了 NSF 的法定使命和通过使用基金会的智力价值和更广泛的影响审查标准进行评估，该项目被认为值得支持。

项目成果

Deterministic Atomic Buffering

确定性原子缓冲

• DOI: 10.1109/micro50266.2020.00083
• 发表时间: 2020-10
• 期刊: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO
• 作者: Chou, Yuan Hsi;Ng, Christopher;Cattell, Shaylin;Intan, Jeremy;Sinclair, Matthew D.;Devietti, Joseph;Rogers, Timothy G.;Aamodt, Tor M.
• 通讯作者: Aamodt, Tor M.

AccelWattch: A Power Modeling Framework for Modern GPUs

AccelWattch：现代 GPU 的功耗建模框架

• DOI: 10.1145/3466752.3480063
• 发表时间: 2021-10-17
• 期刊: MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture
• 作者: Vijay K;iah;iah;Scott Peverelle;Mahmoud Khairy;Junrui Pan;Amogh Manjunath;Timothy G. Rogers;Tor M. Aamodt;Nikolaos Hardavellas
• 通讯作者: Nikolaos Hardavellas

Principal Kernel Analysis: A Tractable Methodology to Simulate Scaled GPU Workloads

主要内核分析：模拟扩展 GPU 工作负载的易处理方法

• DOI: 10.1145/3466752.3480100
• 发表时间: 2021-10-17
• 期刊: MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture
• 作者: Cesar Avalos Baddouh;Mahmoud Khairy;Rol;N. Green;Mathias Payer;Timothy G. Rogers
• 通讯作者: Timothy G. Rogers

Locality-Centric Data and Threadblock Management for Massive GPUs

海量 GPU 的以局部为中心的数据和线程块管理

• DOI: 10.1109/micro50266.2020.00086
• 发表时间: 2020-10-01
• 期刊: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
• 作者: Mahmoud Khairy;Vadim Nikiforov;D. Nellans;Timothy G. Rogers
• 通讯作者: Timothy G. Rogers

Mitigating GPU Core Partitioning Performance Effects

减轻 GPU 核心分区性能影响

• DOI: 10.1109/hpca56546.2023.10070957
• 发表时间: 2023-02-01
• 期刊: 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
• 作者: Aaron Barnes;Fangjia Shen;Timothy G. Rogers
• 通讯作者: Timothy G. Rogers