SHF: Small: Architectural Synthesis for Programmable Accelerators

SHF：小型：可编程加速器的架构综合

• 批准号: 1909661
• 负责人: Zhiru Zhang
• 金额: $ 48.41万
• 依托单位: Cornell University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-07-01 至 2023-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1909661&HistoricalAwards=false
• 关键词: SHF; Small; Architectural; Synthesis; Programmable

Targeted acceleration of functionality in hardware has shown great promise to bring in orders of magnitude improvement in computational capability for a broad range of applications such as artificial intelligence, autonomous vehicles, web search, and virtual reality. However, it is incredibly time consuming and costly to manually design a hardware accelerator that is both high performance and easily programmable for software. This project aims to develop new design automation framework that can automatically generate a high-quality programmable accelerator from architecture specifications defined in a software program. This project builds on the recent advances in high-level synthesis, which is capable of compiling un-timed behavioral specifications into cycle-accurate register-transfer-level circuits. In contrast to conventional high-level synthesis approaches, the proposed framework generates domain-specific instruction-programmable accelerators as opposed to application-specific fixed-function hardware. This research provides a new class of hardware synthesis infrastructure that integrates domain-specific languages, combinatorial optimization algorithms, and data-driven machine learning capabilities to achieve high quality of results on par with those produced by human experts.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

硬件中有针对性的功能加速已显示出巨大的希望，可以在广泛的应用程序中提高计算能力的数量级，例如人工智能，自动驾驶汽车，网络搜索和虚拟现实。但是，手动设计既具有高性能又易于编程的软件加速器的硬件加速器非常耗时且昂贵。该项目旨在开发新的设计自动化框架，该框架可以自动从软件程序中定义的体系结构规范中生成高质量的可编程加速器。 该项目基于高级合成的最新进展，该项目能够将不合时宜的行为规格汇总到周期精确的寄存器转移级电路中。与常规的高级合成方法相反，所提出的框架生成了特定于域的指令程序可编程的加速器，而不是针对特定应用的固定功能硬件。这项研究提供了一类新的硬件综合基础架构，该基础架构集成了特定于领域的语言，组合优化算法以及数据驱动的机器学习能力，以与人类专家生产的那些相等的成绩取得了高质量的结果。该奖项反映了NSF的法定任务，并通过评估了基金会的智力效果，并以评估符合基金会的范围来进行评估。

项目成果

Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC

使用机器学习从痕迹中提取仲裁逻辑：NoC 案例研究

• DOI: 10.1109/dac18074.2021.9586301
• 发表时间: 2021
• 期刊: ACM/IEEE Design Automation Conference (DAC
• 作者: Zhou, Yuan;Wang, Hanyu;Yin, Jieming;Zhang, Zhiru
• 通讯作者: Zhang, Zhiru

A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems

• DOI: 10.1109/tcad.2021.3103825
• 发表时间: 2022-06
• 期刊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• 影响因子: 2.9
• 作者: Lin Cheng;Peitian Pan;Zhongyuan Zhao;Krithik Ranjan;Jack Weber;Bandhav Veluri;Seyed Borna Ehsani;Max Ruttenberg;Dai Cheol Jung;Preslav Ivanov;D. Richmond;M. Taylor;Zhiru Zhang;C. Batten

Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations

• DOI: 10.1109/hpca47549.2020.00062
• 发表时间: 2020-02
• 期刊: 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)
• 作者: Nitish Srivastava;Hanchen Jin;Shaden Smith;Hongbo Rong;D. Albonesi;Zhiru Zhang

SuSy: a programming model for productive construction of high-performance systolic arrays on FPGAs

SuSy：用于在 FPGA 上高效构建高性能脉动阵列的编程模型

• DOI: 10.1145/3400302.3415644
• 发表时间: 2020
• 期刊: Proceedings of the 39th International Conference on Computer-Aided Design
• 作者: Lai, Yi-Hsiang;Rong, Hongbo;Zheng, Size;Zhang, Weihao;Cui, Xiuping;Jia, Yunshan;Wang, Jie;Sullivan, Brendan;Zhang, Zhiru;Liang, Yun
• 通讯作者: Liang, Yun

MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product

• DOI: 10.1109/micro50266.2020.00068
• 发表时间: 2020-10
• 期刊: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
• 作者: Nitish Srivastava;Hanchen Jin;Jie Liu-;D. Albonesi;Zhiru Zhang