SHF: Small: Acceleration Using Smart Memory-on-Chip

SHF：小型：使用智能片上存储器进行加速

• 批准号: 1908601
• 负责人: Reetuparna Das
• 金额: $ 45万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-10-01 至 2024-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1908601&HistoricalAwards=false
• 关键词: SHF; Small; Acceleration; Using; Smart

Memory-on-Chip structures are used in almost all modern computer processing chips, both general-purpose as well as accelerators chips. They occupy a large fraction of the die area, for example, in Intel's server class Xeon processor devotes 35 MB just for its last-level cache, while Google's Tensor Processing Unit dedicates 24 MB for on-chip storage. Furthermore, a processor spends disproportionately large fraction of time and energy in moving data over its memory hierarchy, and in instruction processing, as compared to actual computation. To tackle these inefficiencies, this project proposes a novel idea: re-purpose the elements in memory structures and transform them into large data-parallel compute units. Outcomes of this research have the potential to accelerate computing operations involving heavy use of data sets.Data stored in on-chip memory arrays share wires (bit-lines) and signal sensing apparatus (senseamps). The research is grounded in the obeservation that arithmetic operations can be computed over these shared structures by augmenting a few gates to them. This in-SRAM computing technique is referred to as bit line computing. The preliminary work has demonstrated the potential and feasibility of smart memory-on-chip. This project will explore novel vertically integrated solutions that explore broad use of smart memory-on-chip. The research will develop new operation primitives, programming framework and compiler for smart memories, design neural computing architectures, investigate utilizing smart memories in Application Specific Integrated Circuits (ASICs) and reconfigurable Field Programmable Gate Arrays (FPGAs), and explore the applicability to emerging embedded nonvolatile technologies.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

片上存储器结构几乎用于所有现代计算机处理芯片，包括通用芯片和加速器芯片。它们占据了芯片面积的很大一部分，例如，在英特尔的服务器级 Xeon 处理器中，仅将 35 MB 用于最后一级缓存，而 Google 的张量处理单元则将 24 MB 用于片上存储。此外，与实际计算相比，处理器在其内存层次结构上移动数据以及指令处理上花费了不成比例的大量时间和精力。为了解决这些低效率问题，该项目提出了一个新想法：重新利用内存结构中的元素，并将它们转换为大型数据并行计算单元。这项研究的成果有可能加速涉及大量使用数据集的计算操作。存储在片上存储器阵列中的数据共享线路（位线）和信号传感设备（传感放大器）。这项研究的基础是观察到可以通过向这些共享结构增加一些门来计算算术运算。这种 SRAM 内计算技术称为位线计算。前期工作展示了智能片上存储器的潜力和可行性。该项目将探索新颖的垂直集成解决方案，探索智能片上存储器的广泛使用。该研究将为智能存储器开发新的操作原语、编程框架和编译器，设计神经计算架构，研究在专用集成电路（ASIC）和可重配置现场可编程门阵列（FPGA）中利用智能存储器，并探索新兴嵌入式的适用性该奖项反映了 NSF 的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs

• DOI: 10.1109/fccm51124.2021.00018
• 发表时间: 2021-05
• 期刊: 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
• 作者: Xiaowei Wang;Vidushi Goyal;Jiecao Yu;V. Bertacco;Andrew Boutros;Eriko Nurvitadhi;C. Augustine;R. Iyer;R. Das

Multi-Layer In-Memory Processing

• DOI: 10.1109/micro56248.2022.00068
• 发表时间: 2022-10
• 期刊: 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)
• 作者: Daichi Fujiki;Alireza Khadem;S. Mahlke;R. Das