SHF: Small: The Compiler-Architecture Solution to the Data Dependent, Circuit-Level Critical-Paths Variations

SHF：小型：针对数据相关、电路级关键路径变化的编译器架构解决方案

• 批准号: 1908488
• 负责人: Simone Campanoni
• 金额: $ 49.97万
• 依托单位: Northwestern University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-10-01 至 2023-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1908488&HistoricalAwards=false
• 关键词: SHF; Small; Compiler; Architecture; Solution

Computing performance translates to opportunities for innovations, which positively impact our society. Systems have experienced a steady performance improvement in the past. Unfortunately, recent developments in the semiconductor industry have made this progress hard to maintain, which has slowed down innovations in science and engineering. System performance depends on the capabilities of the compiler used and the underlying computer architecture. Usually, a compiler can control system activities at the instruction granularity while the underlying architecture hides finer-grained information. The compiler's inability to access fine-grained information, however, limits the overall performance obtainable in future systems. The project's novelty is a new compiler and computer architecture co-design where the latter enables the former to control activities at a much finer granularity compared to what has been explored before. This allows the underlying computer architecture to automatically boost the overall system performance as well as to save energy. The project's impact is to enable programmers to automatically make better use of the commodity processors. With processor performance increased, society will benefit from increased productivity and innovation in all areas involving computation. Recent developments in computer architecture have generated tremendous advances in single-chip core count as well as remarkable performance benefits brought by accelerators. However, Amdahl's Law reminds us that single-thread execution will always be the limiting factor for system performance -- a dire warning considering that the processor industry has fallen well short of the decades old sequential code performance growth trend. The team of researchers found that an important performance roadblock is in the sub-cycle domain where the circuit-level critical path latency depends on the data computed. This project designs a new compiler co-designed with the underlying architecture to access and control data-dependent, circuit-level critical path latencies. The impact of this design is the elimination of sub-cycle performance inefficiencies across the computation stack for commodity processors widely used in the whole computing spectrum, ranging from mobile to high performance computing. Code, data, and results emanating from the project will be maintained publicly at the website: http://users.cs.northwestern.edu/~simonec/SCDVCA.htmlThis award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

计算性能转化为创新机会，这对我们的社会产生积极影响。过去，系统的性能经历了稳定的改进。不幸的是，半导体行业最近的发展使得这种进步难以维持，从而减缓了科学和工程的创新。系统性能取决于所使用的编译器的功能和底层计算机体系结构。通常，编译器可以在指令粒度上控制系统活动，而底层架构则隐藏更细粒度的信息。然而，编译器无法访问细粒度信息，限制了未来系统可获得的整体性能。该项目的新颖之处在于新的编译器和计算机体系结构协同设计，其中后者使前者能够以比之前探索的更精细的粒度控制活动。这使得底层计算机架构能够自动提升整体系统性能并节省能源。该项目的影响是使程序员能够自动更好地利用商品处理器。随着处理器性能的提高，社会将受益于所有涉及计算领域的生产力的提高和创新。 计算机架构的最新发展带来了单芯片核心数量的巨大进步以及加速器带来的显着性能优势。然而，阿姆达尔定律提醒我们，单线程执行将永远是系统性能的限制因素——考虑到处理器行业已经远远落后于几十年前的顺序代码性能增长趋势，这是一个可怕的警告。研究人员团队发现，一个重要的性能障碍位于子周期域，其中电路级关键路径延迟取决于计算的数据。该项目设计了一个与底层架构共同设计的新编译器，用于访问和控制数据相关的电路级关键路径延迟。这种设计的影响是消除了整个计算堆栈中广泛使用的商用处理器的子周期性能低效，从移动计算到高性能计算。该项目产生的代码、数据和结果将在网站上公开维护：http://users.cs.northwestern.edu/~simonec/SCDVCA.html 该奖项反映了 NSF 的法定使命，并通过评估被认为值得支持利用基金会的智力优势和更广泛的影响审查标准。

项目成果

WARDen: Specializing Cache Coherence for High-Level Parallel Languages

WARDen：专门针对高级并行语言的缓存一致性

• DOI: 10.1145/3579990.3580013
• 发表时间: 2023
• 期刊: Proceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization
• 作者: Wilkins, Michael;Westrick, Sam;Kandiah, Vijay;Bernat, Alex;Suchy, Brian;Deiana, Enrico Armenio;Campanoni, Simone;Acar, Umut A.;Dinda, Peter;Hardavellas, Nikos
• 通讯作者: Hardavellas, Nikos

EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction Caching

• DOI: 10.1145/3579371.3589097
• 发表时间: 2023-06
• 期刊: Proceedings of the 50th Annual International Symposium on Computer Architecture
• 作者: N. P. Nagendra;Bhargav Reddy Godala;Ishita Chaturvedi;Atmn Patel;Svilen Kanev;Tipp Moseley;Jared Stark;Gilles A. Pokam;Simone Campanoni;David I. August

NOELLE Offers Empowering LLVM Extensions

NOELLE 提供强大的 LLVM 扩展

• DOI: 10.1109/cgo53902.2022.9741276
• 发表时间: 2022
• 期刊: 2022 IEEE/ACM International Symposium on Code Generation and Optimization (CGO
• 作者: Matni, Angelo;Deiana, Enrico Armenio;Su, Yian;Gross, Lukas;Ghosh, Souradip;Apostolakis, Sotiris;Xu, Ziyang;Tan, Zujun;Chaturvedi, Ishita;Homerding, Brian
• 通讯作者: Homerding, Brian

CARAT: a case for virtual memory through compiler- and runtime-based address translation

CARAT：通过基于编译器和运行时的地址转换实现虚拟内存的案例

• DOI: 10.1145/3385412.3385987
• 发表时间: 2020
• 期刊: Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI
• 作者: Suchy, Brian;Campanoni, Simone;Hardavellas, Nikos;Dinda, Peter
• 通讯作者: Dinda, Peter

WARio: efficient code generation for intermittent computing

• DOI: 10.1145/3519939.3523454
• 发表时间: 2022-06
• 期刊: Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation
• 作者: Vito Kortbeek;Josiah D. Hester;Simone Campanoni