SHF:Small:New models, design, and test methods for long-term aging of nanometer VLSI

SHF：Small：纳米VLSI长期老化的新模型、设计和测试方法

• 批准号: 1719047
• 负责人: Sandeep Gupta
• 金额: $ 44万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-08-15 至 2023-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1719047&HistoricalAwards=false
• 关键词: SHF; Small; New; models; design

Transistor aging refers to the phenomenon that a transistor degrades with use over time. Hence, as digital chips are used, transistor aging reduces their performance and increases power consumption. Aging also causes some chips to fail prematurely during their expected lifetimes (called lifetime failures). Since such failures can corrupt user data, cause expensive system downtime, and require expensive maintenance, industry practice requires lifetime failure rates to be of the order of 10 to 100 parts per million. This project will develop completely new methods and CAD tools for design and testing of digital chips to combat aging in uniquely efficient ways. These new methods and tools will dramatically improve yield, dramatically reduce power, and provide chips with extremely low lifetime failure rates, even as aging continues to grow in severity as we approach the end of Moore's Law. In turn, the society at large will reap significant benefits of this research, since lower cost digital systems with low lifetime failure rates will help improve many essential services, especially health, security, and finance. In addition, this project will train students and industry experts in the art and science of aging and its mitigation and prepare them for the era near and beyond the end of Moore's Law. Also, significant outreach effort will ensure that undergraduate students and students from groups underrepresented in STEM will participate in this research.This project has identified and will address three major limitations of existing aging research: serious inaccuracies of existing models in estimating long-term aging for real-life chip usage, the inability of existing memory designs to combat the most common type of memory aging, namely asymmetric aging, and the fact that existing approaches for post fabrication chip testing either provide extremely low yields or unacceptability high lifetime failure rates due to aging. Specifically, this project will develop completely new methods and tools for aging, demonstrate their effectiveness via extensive simulation studies and experiments on test chips, disseminate results and share new tools with academic and industry experts, and train students.

晶体管老化是指晶体管随着使用时间的推移而退化的现象。因此，随着数字芯片的使用，晶体管老化会降低其性能并增加功耗。老化还会导致某些芯片在其预期寿命期间过早失效（称为寿命失效）。由于此类故障可能会损坏用户数据、导致昂贵的系统停机时间并需要昂贵的维护费用，因此行业实践要求生命周期故障率约为百万分之 10 至 100。该项目将开发全新的方法和 CAD 工具来设计和测试数字芯片，以独特有效的方式对抗老化。这些新方法和工具将显着提高产量，显着降低功耗，并为芯片提供极低的寿命故障率，即使随着摩尔定律的终结，老化的严重程度继续加剧。反过来，整个社会也将从这项研究中获益匪浅，因为成本较低、寿命故障率较低的数字系统将有助于改善许多基本服务，特别是健康、安全和金融。此外，该项目还将对学生和行业专家进行衰老及其缓解的艺术和科学方面的培训，让他们为摩尔定律即将结束和结束后的时代做好准备。此外，大量的外展工作将确保本科生和来自 STEM 中代表性不足群体的学生参与这项研究。该项目已确定并将解决现有老龄化研究的三个主要局限性：现有模型在估计长期老龄化方面严重不准确。现实生活中的芯片使用情况、现有存储器设计无法应对最常见的存储器老化类型（即不对称老化），以及用于后制造芯片测试的现有方法要么提供极低的产量，要么由于以下原因导致不可接受的高寿命故障率：老化。具体来说，该项目将开发全新的老化方法和工具，通过在测试芯片上进行广泛的模拟研究和实验来证明其有效性，传播结果并与学术和行业专家共享新工具，并对学生进行培训。

项目成果

HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks

HW-BCP：适用于大型基准的单芯片实施的 SAT 定制硬件加速器

• DOI: 10.1145/3394885.3431413
• 发表时间: 2021-01
• 期刊: 26th Asia and South Pacific Design Automation Conference (ASPDAC
• 作者: Park, Soowang;Nam, Jae;Gupta, Sandeep K.
• 通讯作者: Gupta, Sandeep K.

Memristor-Specific Failures: New Verification Methods and Emerging Test Problems

忆阻器特定故障：新的验证方法和新出现的测试问题

• DOI: 10.1109/vts52500.2021.9794274
• 发表时间: 2022-04-25
• 期刊: 2022 IEEE 40th VLSI Test Symposium (VTS)
• 作者: B. Biswas;S. Gupta
• 通讯作者: S. Gupta

Aging-resilient SRAM design: an end-to-end framework

抗老化 SRAM 设计：端到端框架

• DOI: 10.1109/vts48691.2020.9107571
• 发表时间: 2020-04-01
• 期刊: 2020 IEEE 38th VLSI Test Symposium (VTS)
• 作者: X. Zuo;S. Gupta
• 通讯作者: S. Gupta

Asymmetric sizing: An effective design approach for SRAM cells against BTI aging

不对称尺寸：SRAM 单元抗 BTI 老化的有效设计方法

• 发表时间: 2017-01
• 期刊: 2017 IEEE 35th VLSI Test Symposium (VTS
• 作者: Zuo, Xuan;Gupta, Sandeep
• 通讯作者: Gupta, Sandeep

Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable)

实现单位面积产量最大化的缓存设计：带禁用功能的可切换备用列 (SSC-Disable)

• DOI: 10.1109/vts.2019.8758652
• 发表时间: 2019-04-23
• 期刊: 2019 IEEE 37th VLSI Test Symposium (VTS)
• 作者: Soowang Park;S. Gupta
• 通讯作者: S. Gupta