SaTC: STARSS: Small: Collaborative: Managing Hardware Security in Three-Dimensional Integrated Circuits

SaTC：STARSS：小型：协作：管理三维集成电路中的硬件安全

• 批准号: 1717306
• 负责人: Emre Salman
• 金额: $ 14.67万
• 依托单位: SUNY at Stony Brook
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-10-01 至 2021-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1717306&HistoricalAwards=false
• 关键词: SaTC; STARSS; Small; Collaborative; Managing

Vertically stacked three-dimensional (3D) integration of semiconductor chips is an emerging technology to ensure continued growth in transistor density and performance of integrated circuits (ICs). Despite the well-characterized advantages and limitations, the hardware security of such circuits has not received much attention. With shrinking number of trusted circuit manufacturers, trustworthiness of electronic devices is a growing concern. Vertical integration brings unexplored and unique challenges in managing hardware security. This research develops a cross-layer framework to manage and guarantee hardware security in 3D ICs. The systematic framework developed by this research assesses and enhances trustworthiness of 3D ICs for both commercial and defense-specific applications. Proposed project also supports diverse educational and outreach programs with emphasis on underrepresented groups in both New Hampshire and Stony Brook, Long Island. Existing hardware security solutions are for 2D ICs manufactured by a trusted foundry. Unfortunately, new security problems arise when multiple dies from different vendors are stacked in a 3D IC. Proposed research targets these security weaknesses with an emphasis on the trustworthiness of vertical communications. Solution mechanisms to prevent attacks on the vertical communication path will be investigated to achieve secure die-to-die communication. A secure power delivery architecture will be designed to detect small hardware Trojans in any die within the stack. A switching noise analysis based scheme will be investigated to detect malicious behavior in vertical communication paths.

半导体芯片的垂直堆叠三维（3D）集成是一项新兴技术，可确保晶体管密度和集成电路（IC）性能的持续增长。尽管具有明显的优点和局限性，但此类电路的硬件安全性并未受到太多关注。随着可信电路制造商数量的减少，电子设备的可信度越来越受到关注。垂直整合给管理硬件安全带来了前所未有的独特挑战。这项研究开发了一个跨层框架来管理和保证 3D IC 中的硬件安全。本研究开发的系统框架评估并增强了 3D IC 在商业和国防特定应用中的可信度。拟议的项目还支持多样化的教育和外展计划，重点关注新罕布什尔州和长岛石溪的代表性不足的群体。现有的硬件安全解决方案适用于由值得信赖的代工厂制造的 2D IC。不幸的是，当来自不同供应商的多个芯片堆叠在 3D IC 中时，就会出现新的安全问题。拟议的研究针对这些安全弱点，重点是垂直通信的可信度。将研究防止垂直通信路径受到攻击的解决方案机制，以实现安全的芯片间通信。安全电力传输架构将被设计为检测堆栈内任何芯片中的小型硬件木马。将研究基于开关噪声分析的方案来检测垂直通信路径中的恶意行为。

项目成果

Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques

增强逻辑锁定技术的功率分析攻击弹性

• DOI: 10.1109/isvlsi51109.2021.00034
• 发表时间: 2021-07
• 期刊: IEEE Computer Society Annual Symposium on VLSI (ISVLSI
• 作者: Zhang, Zhiming;Miketic, Ivan;Salman, Emre;Yu, Qiaoyan
• 通讯作者: Yu, Qiaoyan

Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration

使用晶体管级单片 3D 集成的节能绝热电路

• 发表时间: 2020-09
• 期刊: IEEE International System-on-Chip Conference (SOCC
• 作者: Miketic, Ivan;Salman, Emre
• 通讯作者: Salman, Emre

PhaseCamouflage: Leveraging Adiabatic Operation to Thwart Reverse Engineering

PhaseCamouflage：利用绝热操作阻止逆向工程

• DOI: 10.1109/tvlsi.2021.3078567
• 发表时间: 2021-07
• 期刊: IEEE Transactions on Very Large Scale Integration (VLSI
• 作者: Miketic, Ivan;Salman, Emre
• 通讯作者: Salman, Emre

Monolithic 3D Integrated Encryption Core

单片 3D 集成加密核心

• 发表时间: 2019-03
• 期刊: Proceedings of the Government Microcircuit Applications & Critical Technology Conference
• 作者: Miketic, Ivan;Salman, Emre
• 通讯作者: Salman, Emre

Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits

配电网络对三维集成电路功率分析攻击的影响

• DOI: 10.1145/3060403.3060501
• 发表时间: 2017-05-10
• 期刊: Proceedings of the Great Lakes Symposium on VLSI 2017
• 作者: Jaya Dofe;Zhiming Zhang;Qiaoyan Yu;Chen Yan;E. Salman
• 通讯作者: E. Salman