SHF: Small: Hardware-Software Co-Designed Coherence: A Complete Coherence Solution for Performance-, Energy-, and Complexity-Efficiency

SHF：小型：硬件-软件协同设计的一致性：针对性能、能源和复杂性效率的完整一致性解决方案

• 批准号: 1619245
• 负责人: Sarita Adve
• 金额: $ 45万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-06-15 至 2021-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1619245&HistoricalAwards=false
• 关键词: SHF; Small; Hardware; Software; Co

As the benefits from transistor scaling slow down, future performance increases in computing systems will increasingly rely on architectural advances. Today processors use parallelism and increasing amounts of specialization to provide this performance growth. An efficient memory hierarchy is key to achieving the full potential of both of these techniques. The coherence protocol and memory consistency model are at the heart of the complexity-, performance-, and energy-efficiency of the memory hierarchy. Unfortunately, across a variety of systems, coherence protocols and consistency models continue to struggle to obtain an appropriate balance between complexity, performance, and energy consumption. Recently, there has been work on hybrid hardware-software co-designed protocols, exemplified by the DeNovo protocol, which takes a different approach, combining the best of pure hardware and pure software protocols. The key insight is that if software is disciplined, then it is possible to design more efficient hardware. Multiple versions of the DeNovo system have successively relaxed the software restrictions. Introducing such a new technology in classrooms to both graduate and undergraduate students will better prepare them for future memory trend and challenges. Disseminating the results of this research via publications, seminars, tutorials etc. will bring new technology awareness to the community and create more synergy among academia and industry. Prior work has established the potential for DeNovo as a general-purpose system with significant advantages over the state-of-the-art. However, this work of necessity has been limited to simple workloads. Consideration of DeNovo as a viable system for widespread industrial adoption requires demonstrating an integrated system that can run complex workloads (e.g., operating systems) and legacy binaries. This project addresses the remaining research issues to achieve this goal. Although this work is driven by considerations for hybrid hardware-software coherence protocols, the intellectual contributions extend beyond those protocols as well; e.g., integrated support for efficient, coherent data accesses using a variety of disciplines ranging from completely unstructured to highly structured, statically analyzable accesses; a systematic exploration of relaxed atomics, a widely accepted difficulty in current memory consistency models; and understanding concurrent data structures and system code in a coherence neutral way.

随着晶体管缩放带来的好处逐渐减少，计算系统未来的性能提升将越来越依赖于架构的进步，而当今处理器使用并行性和不断增加的专业化来提供这种性能增长，而内存层次结构是高效发挥两者全部潜力的关键。一致性协议和内存一致性模型是内存层次结构的复杂性、性能和能源效率的核心，不幸的是，在各种系统中，一致性协议和一致性模型仍然难以获得。复杂性、性能之间的适当平衡，最近，出现了混合硬件-软件协同设计协议的工作，以 DeNovo 协议为例，它采用了不同的方法，结合了纯硬件和纯软件协议的优点。有了纪律，就有可能设计出更高效的硬件。DeNovo 系统的多个版本已经陆续放宽了软件限制，向研究生和本科生引入这样的新技术，将使他们更好地为未来的记忆趋势和挑战做好准备。传播这项研究的成果将通过出版物、研讨会、教程等方式为社区带来新的技术意识，并在学术界和工业界之间产生更多的协同作用。​之前的工作已经确定了 DeNovo 作为通用系统的潜力，与现有的系统相比具有显着优势然而，这项工作必须仅限于简单的工作负载，将 DeNovo 视为广泛工业采用的可行系统需要展示一个可以运行复杂工作负载（例如操作系统）和遗留系统的集成系统。该项目解决了实现这一目标的剩余研究问题，尽管这项工作是出于对混合硬件-软件一致性协议的考虑而推动的，但其智力贡献也超出了这些协议的范围，例如，对使用的高效一致性数据访问的集成支持。各种学科，从完全非结构化到高度结构化、可静态分析的访问；对宽松原子的系统探索，这是当前内存一致性模型中广泛接受的困难；以及以一致性中立的方式理解并发数据结构和系统代码。