SHF: Small: Collaborative Research: Design of Many-core NoCs for the Dark Silicon Era

SHF：小型：协作研究：暗硅时代的多核 NoC 设计

• 批准号: 1619456
• 负责人: Lizhong Chen
• 金额: $ 35万
• 依托单位: Oregon State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-07-01 至 2020-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1619456&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Design

The proliferation of computing systems of various forms and scales have significantly advanced science, technology, discovery and society at large for the benefit of human kind. As the key building blocks of current and future computing systems, including the Internet of Things, many-core chip multiprocessors (CMPs) are facing unprecedented power challenges brought on by limits in Dennard scaling. This necessitates many-core chips to be designed with the ability to power down on-chip resources to effectively provide scalable performance while keeping power and energy consumption proportional to computing load. This necessity leads to considerable portions of many-core chips having to go dark, thus ushering in the era of dark silicon. To facilitate dark silicon computing, not only computational resources (i.e., processor cores) but also communication resources (i.e., networks on chips, or NoCs) used to connect the computational resources must be developed that can be powered up or down proportionally with performance scalability in response to prevailing load.This research investigates new opportunities, significant challenges, and innovative solutions for harnessing dark silicon in NoC architectures that meet performance, power and energy requirements in the dark silicon era. The objective is to enable non-essential NoC routers to be powered down when needed as well as to enable a corresponding maximum number of routers and router components to be powered down for a given reduction in the number of powered-up processor cores in order to provide energy-proportional, low-power, on-chip communication. Among some of the specific lines of research that are explored are alternative topologies and coordinated routing algorithms to enable more efficient power-gating of NoC routers, holistic approaches for exploiting coordination between the NoC and other on-chip system components as well as factoring in key application characteristics, and novel packet-oriented dynamic power control schemes that explore energy-saving opportunities beyond the conventionally targeted low-load traffic region. Beyond its technical contributions that can impact fundamental advancement in dark silicon computing, this research also has impact more broadly on research education and outreach. Findings from this research are incorporated into graduate curriculum, courses, and undergraduate research experiences. Outreach activities to broaden participation in computing of persons from diverse backgrounds and development levels are also featured.

各种形式和规模的计算系统的激增极大地促进了科学、技术、发现和整个社会的进步，造福于人类。作为当前和未来计算系统（包括物联网）的关键构建模块，多核芯片多处理器 (CMP) 正面临着 Dennard 扩展限制带来的前所未有的功耗挑战。这就需要设计多核芯片，使其能够关闭片上资源，以有效提供可扩展的性能，同时保持功耗和能耗与计算负载成正比。这种必要性导致相当一部分多核芯片不得不变暗，从而迎来了暗硅时代。为了促进暗硅计算，不仅必须开发计算资源（即处理器核心），还必须开发用于连接计算资源的通信资源（即片上网络或NoC），这些资源可以根据性能可扩展性按比例加电或断电这项研究调查了在 NoC 架构中利用暗硅的新机遇、重大挑战和创新解决方案，以满足暗硅时代的性能、功率和能源要求。目标是在需要时使非必要的 NoC 路由器断电，并在给定的加电处理器核心数量减少的情况下使相应最大数量的路由器和路由器组件断电，以便提供能量均衡、低功耗、片上通信。正在探索的一些具体研究方向包括替代拓扑和协调路由算法，以实现更高效的 NoC 路由器电源门控、利用 NoC 和其他片上系统组件之间的协调以及考虑关键因素的整体方法。应用特性，以及新颖的面向数据包的动态功率控制方案，探索超出传统目标低负载流量区域的节能机会。除了可以影响暗硅计算根本性进步的技术贡献之外，这项研究还对研究教育和推广产生更广泛的影响。这项研究的结果被纳入研究生课程、课程和本科生研究经验中。旨在扩大来自不同背景和发展水平的人们参与计算的外展活动也很重要。