I-Corps: Sygnal: Compact, Low Power, High Performance Digital Circuits using Threshold Logic

I-Corps：Sygnal：使用阈值逻辑的紧凑、低功耗、高性能数字电路

• 批准号: 1565921
• 负责人: Sarma Vrudhula
• 金额: $ 5万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-11-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1565921&HistoricalAwards=false
• 关键词: Corps; Sygnal; Compact; Low; Power

Digital circuits made up of transistors are the components inside computer chips that operate nearly all the computing devices (e.g. servers, desktops, laptops, tablets, smartphones, and wearables) in use today. Although we can pack more than a billion transistors in one square centimeter, it is becoming increasingly difficult to make full use of them because they consume too much energy. Today, methods to lower the energy consumption always come with a price?reduced speed, which in turn makes them less capable to perform more challenging tasks (e.g. face recognition by smartphone). This team has developed a new way to design digital circuits that consume much less energy (ranging from 20% to 40%) without sacrificing performance and can be made smaller. Thus the proposed technology will reduce energy consumption of digital systems, extend the battery life and/or improve the capabilities of laptops, tablets, smartphones and other battery powered systems. Another significant advantage of the proposed circuits is that they can be designed with the same commercial tools and the same semiconductor fabrication processes that are used by companies today, enabling easy and rapid adoption by industry. High performance, low-­‐power digital circuits are required for a large class of products including smartphones and wearables. Current semiconductor solutions rely on clock and power management to reduce energy consumption, but reduction in energy per operation has relied on technology scaling with diminishing returns. This I-Corps team has developed a digital circuit implementation technology, that reduces joules/operation and area without compromising speed, and is based on three fundamental advances in CMOS logic design, all patent protected. (1) Robust, low power threshold logic circuit design, (TLG), that combines the functionality of a large set of complex functions, and a flip-­‐flop into a single cell. (2) A standard cell library of TLGs, which is perfectly compatible with conventional cell libraries used by commercial synthesis, optimization and physical design tools. (3) Software that optimizes a given logic network using cells and conventional logic cells, resulting in a hybrid design. All three - the circuit architecture, cell library and design software - were designed to ensure 100% compatibility with existing commercial design flows, allowing fully automated synthesis, optimization and layout using commercial tools.

由晶体管组成的数字电路是计算机芯片内部的组件，可运行当今使用的几乎所有计算设备（例如服务器、台式机、笔记本电脑、平板电脑、智能手机和可穿戴设备），尽管我们可以在一个正方形中容纳超过 10 亿个晶体管。厘米，充分利用它们变得越来越困难，因为它们消耗太多能量。如今，降低能耗的方法总是以降低速度为代价，这反过来又使它们无法执行更具挑战性的任务。 （例如智能手机的人脸识别）。该团队开发了一种新的数字电路设计方法，可以在不牺牲性能的情况下消耗更少的能量（从 20% 到 40%），因此所提出的技术将减少能耗。所提出的电路的另一个显着优点是它们可以使用相同的商业工具和相同的半导体制造工艺进行设计。那如今，许多公司都在使用高性能、低功耗的数字电路，包括智能手机和可穿戴设备。当前的半导体解决方案依靠时钟和电源管理来降低能耗。每次操作能耗的降低依赖于收益递减的技术扩展。该 I-Corps 团队开发了一种数字电路实现技术，可在不影响速度的情况下减少焦耳/操作和面积，并且基于 CMOS 逻辑的三个基本进步。设计，所有专利均受保护。 (1) 稳健、低功耗阈值逻辑电路设计 (TLG)，将大量复杂功能和触发器组合到单个单元中。 TLG 与商业综合、优化和物理设计工具使用的传统单元库完美兼容。 (3) 使用单元和传统逻辑单元优化给定逻辑网络的软件，从而实现所有三者的混合设计。 , 细胞库和设计软件 - 旨在确保与现有商业设计流程 100% 兼容，允许使用商业工具进行全自动合成、优化和布局。