SHF: Small: Improving Memory Performance on Fused Architectures through Compiler and Runtime Innovations

SHF：小型：通过编译器和运行时创新提高融合架构的内存性能

• 批准号: 1525609
• 负责人: Xipeng Shen
• 金额: $ 47万
• 依托单位: North Carolina State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-08-01 至 2020-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1525609&HistoricalAwards=false
• 关键词: SHF; Small; Improving; Memory; Performance

During the past decade, accelerators such as Graphics Processing Units (GPUs) have entered the area of general-purpose computing. They are now widely used for achieving high performance in scientific simulation, business analytics, image processing, and many other application domains. Their effectiveness however has been largely constrained by narrow and slow interconnections to multicore CPUs. Instead of such disjoint memories for multicore CPUs on one side and GPUs on the other, contemporary architectures are adopting an integrated design: Conventional CPUs and co-accelerators are integrated on the same die with access to the same memory. The integration provides new opportunities for synergistic execution on CPUs and GPUs, but can also intensify resource contention within the memory hierarchy. The implications yet remain to be understood.This project aims to systematically explore the new challenges and opportunities of the integration, especially for compilers and runtime systems in governing program transformations and maintaining them at runtime for data locality, task partitioning and scheduling. The PIs propose to advance the state of the art by promoting synergistic execution in support of data sharing while creating spheres of isolation between CPU and GPU execution to mitigate resource contention of non-shared data. The proposed techniques include a set of novel compiler transformations, concurrent program control and data abstractions, and systems mechanisms that fostersharing and reduce cross-boundary contention depending on memory access patterns with respect to shared hardware resources. This synergy between compiler techniques and the runtime system has the potential to significantly improve performance and power guarantees for co-scheduling program fragments on fused architectures.

在过去的十年中，图形处理单元（GPU）等加速器已经进入通用计算领域。它们现在广泛用于在科学模拟、业务分析、图像处理和许多其他应用领域实现高性能。然而，它们的有效性在很大程度上受到与多核 CPU 的狭窄且缓慢的互连的限制。现代架构不再采用一侧多核 CPU、另一侧 GPU 的分离存储器，而是采用集成设计：传统 CPU 和辅助加速器集成在同一芯片上，可访问同一存储器。这种集成为 CPU 和 GPU 上的协同执行提供了新的机会，但也可能加剧内存层次结构内的资源争用。其影响仍有待理解。该项目旨在系统地探索集成的新挑战和机遇，特别是编译器和运行时系统在管理程序转换并在运行时维护它们以实现数据局部性、任务分区和调度。 PI 建议通过促进协同执行来支持数据共享，同时在 CPU 和 GPU 执行之间创建隔离范围以减轻非共享数据的资源争用，从而推进最先进的技术。所提出的技术包括一组新颖的编译器转换、并发程序控制和数据抽象，以及根据共享硬件资源的内存访问模式促进共享和减少跨界争用的系统机制。 编译器技术和运行时系统之间的这种协同作用有可能显着提高融合架构上协同调度程序片段的性能和功率保证。

项目成果

T-Pack: Timed Network Security for Real Time Systems

T-Pack：实时系统的定时网络安全

• DOI: 10.1109/isorc52013.2021.00014
• 发表时间: 2021-06
• 期刊: IEEE International Symposium on Real-Time Computing (ISORC
• 作者: Mittal, Swastik;Mueller, Frank
• 通讯作者: Mueller, Frank