SaTC: STARSS: Design of Secure and Anti-Counterfeit Integrated Circuits

SaTC：STARSS：安全防伪集成电路设计

• 批准号: 1441639
• 负责人: Keshab Parhi
• 金额: $ 33.3万
• 依托单位: University of Minnesota-Twin Cities
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-10-01 至 2018-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1441639&HistoricalAwards=false
• 关键词: SaTC; STARSS; Design; Secure; Anti

Hardware security, whether for attack or defense, differs from software, network, and data security in that attackers may find ways to physically tamper with devices without leaving a trace, and mislead the user to believe that the hardware is authentic and trustworthy. Furthermore, the advent of new attack modes, illegal recycling, and hard-to-detect Trojans make hardware protection an increasingly challenging task. Design of secure hardware integrated circuits requires novel approaches for authentication that are ideally based on multiple layers of protection. This project develops a novel framework for embedding heterogeneity and hierarchy in security and obfuscation at multiple layers into the design of integrated circuits. The project uses a combination of server-based global authentication combined with local authentication of components from third-party vendors reduces communication with the server, thus reducing the communication overhead as well as error in authentication. The investigators explore new approaches to increasing robustness of SRAM based physical unclonable functions (PUFs) by intentional voltage stress, and the tradeoffs in hierarchies of authentication. The project investigates techniques for obfuscation based on modifications of finite state machine (FSM) state transition graphs, and obfuscation metrics that are developed and validated using data collected from test chips.

硬件安全，无论是攻击还是防御，都不同于软件、网络和数据安全，攻击者可能会想方设法对设备进行不留痕迹的物理篡改，误导用户相信硬件是真实可信的。此外，新的攻击模式、非法回收和难以检测的木马的出现使得硬件保护变得越来越具有挑战性。安全硬件集成电路的设计需要理想地基于多层保护的新颖的身份验证方法。该项目开发了一种新颖的框架，用于将多层安全性和混淆的异构性和层次结构嵌入到集成电路设计中。该项目结合使用基于服务器的全局身份验证与第三方供应商组件的本地身份验证相结合，减少了与服务器的通信，从而减少了通信开销以及身份验证错误。研究人员探索了通过有意的电压应力和身份验证层次结构的权衡来提高基于 SRAM 的物理不可克隆功能 (PUF) 鲁棒性的新方法。该项目研究基于有限状态机 (FSM) 状态转换图修改的混淆技术，以及使用从测试芯片收集的数据开发和验证的混淆指标。