SaTC: STARSS: Design of Secure and Anti-Counterfeit Integrated Circuits

SaTC：STARSS：安全防伪集成电路设计

• 批准号: 1441639
• 负责人: Keshab Parhi
• 金额: $ 33.3万
• 依托单位: University of Minnesota-Twin Cities
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-10-01 至 2018-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1441639&HistoricalAwards=false
• 关键词: SaTC; STARSS; Design; Secure; Anti

Hardware security, whether for attack or defense, differs from software, network, and data security in that attackers may find ways to physically tamper with devices without leaving a trace, and mislead the user to believe that the hardware is authentic and trustworthy. Furthermore, the advent of new attack modes, illegal recycling, and hard-to-detect Trojans make hardware protection an increasingly challenging task. Design of secure hardware integrated circuits requires novel approaches for authentication that are ideally based on multiple layers of protection. This project develops a novel framework for embedding heterogeneity and hierarchy in security and obfuscation at multiple layers into the design of integrated circuits. The project uses a combination of server-based global authentication combined with local authentication of components from third-party vendors reduces communication with the server, thus reducing the communication overhead as well as error in authentication. The investigators explore new approaches to increasing robustness of SRAM based physical unclonable functions (PUFs) by intentional voltage stress, and the tradeoffs in hierarchies of authentication. The project investigates techniques for obfuscation based on modifications of finite state machine (FSM) state transition graphs, and obfuscation metrics that are developed and validated using data collected from test chips.

硬件安全性（无论是用于攻击还是防御）与软件，网络和数据安全性的不同之处在于攻击者可能会找到方法可以在不留下跟踪的情况下物理篡改设备，并误导用户相信硬件是真实且可信赖的。此外，新的攻击模式的出现，非法回收和难以检测的木马使硬件保护成为越来越具有挑战性的任务。安全硬件集成电路的设计需要采用新颖的方法来进行身份验证，这是理想情况下基于多层保护的理想方法。该项目开发了一个新颖的框架，用于将多个层的安全性和层次结构嵌入到整体电路的设计中。该项目结合了基于服务器的全局身份验证，结合了第三方供应商的局部对组件的局部身份验证，可以减少与服务器的通信，从而减少通信开销以及身份验证的错误。研究人员探索了通过故意电压压力以及身份验证层次结构的折衷方案来提高基于SRAM的物理不可吻合功能（PUF）的鲁棒性的新方法。该项目根据有限状态机器（FSM）状态过渡图的修改以及使用从测试芯片收集的数据开发和验证的混淆指标，研究了混淆的技术。