SHF: Small: A Brick in the Wall: Achieving Yield, Performance and Density Effective DRAM Beyond 22nm Technology

SHF：小型：墙上的砖：实现超越 22 纳米技术的良率、性能和密度有效 DRAM

• 批准号: 1422331
• 负责人: Jun Yang
• 金额: $ 45万
• 依托单位: University of Pittsburgh
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-07-15 至 2019-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1422331&HistoricalAwards=false
• 关键词: SHF; Small; Brick; Wall; Achieving

For more than four decades, computer main memory has predominantly used Dynamic Random Access Memory (DRAM). This technology is a mature commodity that has been optimized and balanced among cost, performance, capacity and energy. Much of DRAM?s success is due to continuous shrinking of the silicon devices in the memory, which allows DRAM capacity to double roughly every two years, satisfying the aggressive need for more memory capacity of today?s and tomorrow?s applications. Yet, a critical problem lies in the shrinking of the device dimensions: It is coming to a halt largely due to the inability of the manufacturing process to precisely control the sizes of a device, which is termed process variation (PV). There are some known problems with PV. However, a vital problem that has rarely been investigated in the past is that PV can cause critical memory operational timing violations. Such violations slash DRAM chip yield, and immediately increase the chip cost. Solving this challenge is crucial to the future of the DRAM industry, which is highly sensitive to cost and profit.This research aims to address the challenge imposed by PV on DRAM device timing to chip yield. Our key approach is to expose inherit operational timing variations caused by PV, so that they can be managed externally by the memory controller. This approach trades exposed timing variability for enhanced chip yield, without harming chip density, by allowing more DRAM chips to meet design specifications. Since the timing variations lead to application performance loss, we propose a suite of techniques that progressively mitigate the loss arising from increasing variance with deeper technology scaling. Our hypothesis is that the threat to yield loss due to technology scaling and PV can be well controlled with our progressive mechanisms, if existing timing constraints for memory operations can adapt to PV-induced speed variations. The broader impact of this research is to enable the continuous scaling of the DRAM technology to achieve the cost, capacity and performance requirement for future computing in engineering, scientific, biological, environmental, business and consumer applications. Both undergraduate and graduate students will be recruited and trained through research and education opportunities provided by this project.

四十多年来，计算机主存储器主要使用动态随机存取存储器（DRAM）。该技术是一种成熟的商品，在成本、性能、容量和能源之间进行了优化和平衡。 DRAM 的成功很大程度上归功于内存中硅器件的不断缩小，这使得 DRAM 容量大约每两年翻一番，满足了当今和未来应用对更大内存容量的迫切需求。 然而，一个关键问题在于器件尺寸的缩小：它的停滞主要是由于制造过程无法精确控制器件的尺寸，这被称为工艺变化（PV）。 PV 存在一些已知问题。然而，过去很少被研究的一个重要问题是 PV 可能导致严重的内存操作时序违规。此类违规行为会大幅降低 DRAM 芯片产量，并立即增加芯片成本。解决这一挑战对于 DRAM 行业的未来至关重要，因为该行业对成本和利润高度敏感。本研究旨在解决 PV 对 DRAM 器件时序和芯片良率带来的挑战。 我们的关键方法是公开由 PV 引起的继承操作时序变化，以便它们可以由内存控制器进行外部管理。这种方法通过允许更多 DRAM 芯片满足设计规范，以牺牲暴露的时序可变性来提高芯片产量，同时又不会损害芯片密度。由于时序变化会导致应用程序性能损失，因此我们提出了一套技术，可以通过更深层次的技术扩展来逐步减轻因方差增加而带来的损失。我们的假设是，如果现有的内存操作时序限制能够适应 PV 引起的速度变化，那么由于技术扩展和 PV 造成的良率损失威胁可以通过我们的渐进机制得到很好的控制。这项研究的更广泛影响是使 DRAM 技术能够不断扩展，以满足工程、科学、生物、环境、商业和消费者应用中未来计算的成本、容量和性能要求。本科生和研究生都将通过该项目提供的研究和教育机会来招募和培训。

项目成果

D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory

D-ORAM：路径 ORAM 委派，可在具有不可信内存的云服务器上实现低执行干扰

• DOI: 10.1109/hpca.2018.00043
• 发表时间: 2018-02-01
• 期刊: 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)
• 作者: Rujia Wang;Youtao Zhang;Jun Yang
• 通讯作者: Jun Yang

PEP: Proactive Checkpointing for Efficient Preemption on GPUs

PEP：主动检查点以实现 GPU 上的高效抢占

• DOI: 10.1109/dac.2018.8465929
• 发表时间: 2018-06
• 期刊: 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC
• 作者: Li, Chen;Yang, Jun;Zigerelli, Andrew;Guo, Yang
• 通讯作者: Guo, Yang

A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network

纳米光子片上网络的工艺变化容忍方法

• DOI: 10.1145/3208073
• 发表时间: 2018-07
• 期刊: ACM Journal on Emerging Technologies in Computing Systems
• 影响因子: 2.2
• 作者: Xu, Yi;Yang, Jun;Melhem, Rami
• 通讯作者: Melhem, Rami

Enabling Intra-Plane Parallel Block Erase in NAND Flash to Alleviate the Impact of Garbage Collection

在 NAND 闪存中启用平面内并行块擦除以减轻垃圾收集的影响

• DOI: 10.1145/3218603.3218627
• 发表时间: 2018-07-23
• 期刊: Proceedings of the International Symposium on Low Power Electronics and Design
• 作者: Tyler Garrett;Jun Yang;Youtao Zhang
• 通讯作者: Youtao Zhang

Boosting chipkill capability under retention-error induced reliability emergency

提高保留错误引起的可靠性紧急情况下的芯片消除能力

• DOI: 10.1145/3287624.3287639
• 发表时间: 2019-01
• 期刊: Proceedings of the 24th Asia and South Pacific Design Automation Conference
• 作者: Zhang, Xianwei;Wang, Rujia;Zhang, Youtao;Yang, Jun
• 通讯作者: Yang, Jun