EAGER:CCF: Transient Architectures for Energy Efficient Computation

EAGER：CCF：节能计算的瞬态架构

• 批准号: 1417323
• 负责人: Sudhakar Yalamanchili
• 金额: $ 30万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-03-01 至 2017-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1417323&HistoricalAwards=false
• 关键词: EAGER; CCF; Transient; Architectures; Energy

To sustain performance scaling with the continued progression of Moore?s Law in deep nanometer nodes, we must seek new and innovative advances in energy efficient computing architectures. Such advances are central to the effective operation of all modern processors in platforms ranging from mobile devices to data centers and high-performance computing (HPC) machines that drive national initiatives in key areas such as science, finance, and defense. The major determinants of power consumption are voltage and frequency. The continuing need to scale energy efficiency in the presence of time-varying application workloads increases the number of fine grained power states as well as the frequency of power state transitions in future processors. However, rapid and fine-grained power state transitions increases the time spent in power state transitions as a percentage of the execution time. Thus unchallenged, designers will soon be faced with an impossible choice between energy efficiency (increasing frequency of transitions) and performance loss (time spent in making transitions). However, sustaining performance scaling will need concurrent advances in both.Transient architectures developed in this proposal aim to address this challenge. These are processor microarchitectures that can continue to perform useful computation during power state transitions. The challenges lay in the fact that during power state transitions the supply voltage received by a logic circuit is not stable for a finite duration. Conventionally, a synchronous digital circuit cannot operate correctly when the supply voltage is varying, making execution unreliable during this unstable period. The transient architectures aim to perform useful computation even under unstable supply during these power state transitions by employing a unique combination of innovative power regulation circuits, adaptive computational circuits, and processor microarchitecture technologies. The key concepts enable computational circuits to ramp up to full speed operation in concert with supply voltage transition thereby performing useful computation during power state transitions. The operational principles underlying transient architectures will be demonstrated via silicon test chips and micro-architectural simulations. This departure from conventional thinking can transform the state of the practice in the design of power and energy efficient processor microarchitectures leading to new ultra-low power designs with superior energy-performance tradeoffs than the state of the practice.

为了随着摩尔定律在深纳米节点中的持续发展而维持性能扩展，我们必须在节能计算架构方面寻求新的创新进步。 这些进步对于从移动设备到数据中心和高性能计算 (HPC) 机器等平台上的所有现代处理器的有效运行至关重要，这些平台推动了科学、金融和国防等关键领域的国家举措。功耗的主要决定因素是电压和频率。在存在时变应用程序工作负载的情况下，不断需要扩展能源效率，这增加了未来处理器中细粒度电源状态的数量以及电源状态转换的频率。 然而，快速且细粒度的电源状态转换会增加电源状态转换所花费的时间占执行时间的百分比。因此，毫无疑问，设计人员很快将面临能源效率（增加转换频率）和性能损失（转换所花费的时间）之间的不可能选择。然而，维持性能扩展需要两者同时进步。本提案中开发的瞬态架构旨在解决这一挑战。这些处理器微架构可以在电源状态转换期间继续执行有用的计算。挑战在于，在电源状态转换期间，逻辑电路接收到的电源电压在有限的时间内不稳定。传统上，当电源电压变化时，同步数字电路无法正确运行，从而导致在此不稳定期间执行不可靠。瞬态架构旨在通过采用创新功率调节电路、自适应计算电路和处理器微架构技术的独特组合，即使在电源状态转换期间电源不稳定的情况下也能执行有用的计算。这些关键概念使计算电路能够与电源电压转换一起加速到全速运行，从而在电源状态转换期间执行有用的计算。瞬态架构的工作原理将通过硅测试芯片和微架构模拟进行演示。这种与传统思维的背离可以改变功率和节能处理器微架构设计的实践状态，从而带来新的超低功耗设计，并具有比实践状态更优越的能源性能权衡。