GOALI: Power-Efficient, High-Resolution, Analog-to-Digital Converter for Broadband Applications

GOALI：适用于宽带应用的高能效、高分辨率、模数转换器

• 批准号: 1404890
• 负责人: Jose Silva-Martinez
• 金额: $ 35万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-08-15 至 2018-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1404890&HistoricalAwards=false
• 关键词: GOALI; Power; Efficient; Resolution; Analog

Proposal No:1404890GOALI: Power-Efficient, High-Resolution, Analog-to-Digital Converter for RF-to-Digital Applications That Digitize Up to 1 GHz Bandwidth with Low Power ConsumptionJose Silva-MartinezTexas A&M UniversityAbstract:This project promises to improve the power efficiency, bandwidth and resolution of real-world analog signals with processing made possible by the development of a novel analog-to-digital converter with an unmatched architecture that will have a significant impact on extending the battery lifetime and reliability of electronic devices, and it also has the potential to reduce the production cost of mixed-mode systems on chips. Currently more than 2.7 billion users demand a global network capacity of several trillions of bits per second. Smaller feature size transistors in CMOS technology allow more digital functions in a single chip making possible the physical realization of more complex signal processing algorithms that were prohibited in the recent past. The "All in One" mobile systems are clearly becoming the preferred source of communication. For instance, emerging Long-Term Evolution (LTE) standards for the next generation of cellular phones have been developed to allocate more and faster services. Applications such as entire digitization of the newly deployed digital TV channels, high resolution image recognition as well as a number of military applications require wide-band and high resolution digitizers, usually requiring over 12 effective number of bits. This project is a step towards the digitization of multiple services. Consumer electronics, wireless communication and image processing industries as well as homeland security and military sectors will benefit from the development of high-resolution broadband real-time digitizers.This project is designed to meet future multi-standard application demands with a new highly efficient, high-resolution analog-to-digital converter (ADC) operating in the GHz frequency range. The aim of this project is to develop an ADC architecture that digitizes up to 1 GHz bandwidth with modest power consumption, utilizing minimal digital resources. The proposed time interleave ADC architecture will employ four pipeline sub-ADCs, running at 500 MS/s each to achieve a resolution of 12 effective number of bits at a rate of 2x109 signal samples per second while overall power dissipation is under 500mWatts. This will be possible by leveraging a very fast (40 nm or more) CMOS technology, developing an efficient calibration scheme for better linearity and integrating innovative IC design techniques suitable for high-resolution low-power broadband applications. The input signal is processed by four independent channels that operate in parallel, which then relaxes the requirements for every channel. The main drawback of this approach is the fact that system linearity, and so system performance, is limited by unavoidable mismatches between channels. Inaccuracies when sampling the input signal represents another relevant limitation to system resolution. This research will develop innovative solutions to resolve these existing hurdles and will focus on combining the calibration schemes with through limited-gain but highly-linear amplification stages that should result in greener solutions. High-gain amplifiers will be avoided when possible since they are power hungry and their bandwidth is limited. A new efficient residue curve will be used to further improve sub-ADCs linearity and reduce system power consumption. The proposed architecture is a relevant step towards the realization of efficient RF-to-digital information converters, minimizing the use of noisy and inaccurate analog hardware.

提案编号：1404890Goali：针对RF到数字应用的强力，高分辨率，类似于数字的转换器，可将高达1 GHz带宽数字化，而低功率消耗Jose Jose Jose Jose Jose Jose Jose Jose silva-martineztexas a＆m UniversityAbstract：这个项目有望提高动力通过开发新颖的模拟转换器，具有无与伦比的体系结构，对现实世界中的模拟信号的效率，带宽和分辨率，可以对延长电池寿命和电子设备的可靠性产生重大影响，并且IT将产生重大影响还有可能降低芯片上混合模式系统的生产成本。目前，用户超过27亿用户要求每秒数万亿位的全球网络容量。 CMOS技术中较小的特征大小晶体管允许在单个芯片中更多的数字功能，从而可以实现近期禁止的更复杂的信号处理算法的物理实现。 “全部”移动系统显然已成为沟通的首选来源。例如，已开发出新的蜂窝电话的长期发展标准（LTE）标准，以分配更多和更快的服务。诸如新部署的数字电视频道的全部数字化，高分辨率图像识别以及许多军事应用之类的应用程序需要宽带和高分辨率数字化器，通常需要超过12个有效数量的钻头。该项目是迈向多个服务数字化的一步。消费电子，无线通信和图像处理行业以及国土安全和军事部门将受益于高分辨率宽带实时数字化器的开发。该项目旨在满足未来的多标准申请需求，并具有新的高效，高效，高效在GHz频率范围内运行的高分辨率类似于数字转换器（ADC）。该项目的目的是开发一种ADC体系结构，该体系结构以最少的数字资源为数字化的功耗适中，将多达1 GHz带宽数字化。拟议的时间交流ADC体系结构将采用四个管道子ADC，每个管道子ADC以500 ms/s的速度运行，以每秒2x109信号样本的速率分辨率为12个有效数量的位，而整体功率耗散量低于500MWATT。通过利用非常快速（40 nm或更多）CMOS技术，开发有效的校准方案来更好地线性和整合适用于高分辨率低点宽带应用程序的创新IC设计技术，这将是可能的。输入信号由四个并行操作的独立通道处理，然后放宽每个通道的要求。这种方法的主要缺点是，系统线性及因此系统性能受到通道之间不可避免的不匹配的限制。采样时，不准确表示输入信号代表了系统分辨率的另一个相关限制。这项研究将开发创新的解决方案，以解决这些现有的障碍，并将专注于通过有限的但高线的扩增阶段将校准方案与应导致更绿色的解决方案相结合。由于它们是饥饿的电力，并且其带宽受到限制，因此将避免使用高增益放大器。新的有效残留曲线将用于进一步提高子ADC线性并降低系统功耗。所提出的体系结构是实现有效的RF到数字信息转换器的相关步骤，从而最大程度地减少了嘈杂和不准确的模拟硬件的使用。